[SI-LIST] Re: Memory Signal Integrity
- From: "Michael Rose" <mrose@xxxxxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 21 Sep 2006 11:35:55 -0400
Kenny,
I believe most SDRAM controllers either use an external match delay copy =
of the clock to register read data input or an internal delay that =
represents a nominal one-way flight time to the memory; or as Steve =
mentioned, enough slop so that routing skew doesn't matter. I generally =
probe clock at the memory for reads and probe the data at the =
controller.
Mike
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of steve weir
Sent: Thursday, September 21, 2006 8:03 AM
To: kenny_frohlich@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Memory Signal Integrity
Kenny, you will always need to know the relationship between data and=20
clock at the sampler. So no matter where you look at the clock you=20
will need to normalize it to the die. SDR SDRAM has a lot of slop,=20
so you can tolerate errors in the analysis like looking at the clock=20
a moderate distance away without correction.
Steve.
At 09:12 PM 9/20/2006, Kenny Frohlich wrote:
>Hi Expert,
> I have a question on memory signal integrity:
> For memory write cycle, both data and clock signals are probed at=20
> the memory device (SDRAM).
> For memory read cycle, data signal is probed at the CPU (memory=20
> controller). But where should I probe the clock signal - at the=20
> CPU (source) or at the memory device (destination)? The clock=20
> signal is much cleaner at the memory device.
>
> Thanks,
> Kenny
>
>---------------------------------
>Get your own web address for just $1.99/1st yr. We'll help. Yahoo!=20
>Small Business.
>
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