Hi Waqas,
If your signal's rise time is 1ns or 0.8ns, the signal bandwidth is
around 300-400MHz, so if you really have a 500MHz flat transfer profile
from your probe tips all the way to the scope output, it should be
reasonably good in this case. Since you say you observed something like
a sine wave, it suggests that somewhere along the way very serious band
limitation occurred. As Joe said, the 8pF probe capacitance in itself
creates a band limitation somewhere in the order of 200MHz.
As others pointed out, you can also use a regular volt meter to get the
common mode voltage.
Dont forget to put a 10kohm resistor in series to the signal to isolate
the input capacitance from your circuit.
Regards,
Istvan Novak
Oracle
On 4/1/2015 9:48 AM, waqas chaudhary wrote:
Hi Istvan,
I am using probe which has 500Mhz bandwidth while my scope has 500MHz
bandwindth and 2GS/s sampling rate. I guess this is too low for 100Mhz
oscillator measurement.
This document from SiTime,
http://www.sitime.com/support2/documents/AN10028-Probing-Oscillator-Output.pdf
suggests that I need around 1GHz probe with similar scope with atleast
6GS/s if i assume my oscillator rise time is 1ns while it is actually
at max 0.8ns.
I will try to get better scope and probe.
But still i cannot understand the 0.75V Vcm DC level of single ended
lvds signals. It should be 1.25V as fpga vendor says it provides the
Vcm itself in lvds receiver.
I will try changing internal termination schemes to see if it changes
something but at the moment i am using 100 ohm differential.
Or may be i should just remove the AC caps from the clock net to ease
the simulation measurement correlation and let the DC go from the
oscillator to FPGA.
regards
waqas
On Wed, Apr 1, 2015 at 2:36 PM, Istvan Novak <istvan.novak@xxxxxxxxxxx
<mailto:istvan.novak@xxxxxxxxxxx>> wrote:
Hi Waqas,
First you need to make sure that your probe and probe connection
are suitable for the purpose.
Some 10x passive probes may not have more than a couple of hundred
MHz when you use
the best connection, and the bandwidth gets more limited if you
happen to connect the
probe with grip-clips and wires.
Regards,
Istvan Novak
Oracle
On 4/1/2015 3:48 AM, waqas chaudhary wrote:
Hi experts,
I have a board with 100MHz oscillator LVDS 2.5V *AC coupled*
with 100nF
capacitors to clock input pins of FPGA. Clock is working fine
and programs
are running correctly on FPGA using the oscillator clock.
Problem is in simulation and measurement correlation of the
clock net.
In simulation using IBIS models,
oscillator (+) --> 100nf --> FPGA Clkp
oscillator (-) --> 100nF --> FPGA Clkn
| -----
| |
10M 8pF
| |
-------
gnd
10M and 8pF are to include the effect of probe.
I have internal differential termination Rd = 100ohm on FPGA
between Clkp
and Clkn.
*Simulation result* at fpga side of ac coupling cap: *Vcm = 1.25V*
*Measurement result* using 10x passive probe on 500MHz
oscilloscope . *Vcm
= 0.75V*
As i am a beginner,
i) I need some guidance what i am doing wrong in measuring
the clock net
and why there is so much difference in DC level of single
ended (+) and (-)
clock signals.
ii) Also, my measured signal is looking like a pure sinusoid while
simulation is more like a pulse.
Looking forward to your advice.
Best regards
waqas
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