[SI-LIST] Re: LVDS 2.5V Vcm(common mode) simulation measurement correlation

  • From: Dave Cuthbert <telegrapher9@xxxxxxxxx>
  • To: waqaschaudharyciit@xxxxxxxxx
  • Date: Wed, 8 Apr 2015 09:00:26 -0600

I tell new SI engineers that the first thing to do when a new oscilloscope
arrives is to throw out the 10X hi-z passive probes and use good active
probes or a 500 ohm 10X probe.
On Wed, Apr 8, 2015 at 6:37 AM, waqas chaudhary <
waqaschaudharyciit@xxxxxxxxx> wrote:

Writing this message to archive the solution i found for my problem with AC
Coupled LVDS 100MHz clock to FPGA clock input pins.
*Problem 1*: Low Vcm of 0.75V measured. Simulation gave 1.2V which i am not
sure if it was correct even.
*Solution*: Removed the AC caps from board and put 0 ohm resistors
instead. DC level is exactly as in simulation i.e 1.25V. Board works fine
and FPGA PLL gets locked.

*Problem 2*: Shape of input clock was measured like a sine wave. I was
putting the Ground connection of probe through Ground lead to a bit far
point on a connector on board with alligator clip.
*Solution* : Same probe 10x 500Mhz with 8pF input capacitance used but now
removed the ground lead and instead put a wire around the ground connection
on probe to a close GND via on the board. Now , wave looks exactly as in
simulation that is a pulse wave of 100MHz.

Lession i learnt: Always put ground connection of probe close to
measurement point with shortest wire as possible !

Thanks to all who gave me the idea of checking the ground connection of
probe and DC coupling the clock net.

Best regards
waqas

On Thu, Apr 2, 2015 at 6:44 PM, Tom Dagostino <tom@xxxxxxxxxxxxxxxxx>
wrote:

Orin

When scope manufacturers specify a probe bandwidth they have the
condition
that the probe is attached to a specific scope and the bandwidth seen at
the
probe tip (using a special fixture with no inductance, 25 Ohm source
impedance, etc.) is what is observed on the scope. I used to work for
Tek
and that is how we did it. I'm sure the other major scope vendors use
similar criteria.

Tom Dagostino

Teraspeed Labs
9999 SW Wilshire Street
Suite 102
Portland, OR 97225

tom@xxxxxxxxxxxxxxxxx
www.teraspeedlabs.com

971-279-5325 office
503-430-1065 cell


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Orin Laney
Sent: Wednesday, April 01, 2015 7:29 PM
To: istvan.novak@xxxxxxxxxxx; 'waqas chaudhary'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LVDS 2.5V Vcm(common mode) simulation measurement
correlation

Imputing risetime from bandwidth, and noting that single pole risetimes
add
as the root of the sum of the squares, cascading two devices each with
500
MHz 3 dB points yields a cascaded 3 dB bandwidth around 350 MHz.
Fortunately, most scopes are conservatively rated, but still you will do
best to use a probe with a bandwidth much higher than that of the scope
if
you want to see results commensurate with the bandwidth of the scope. Why
do
we persist in using XX bandwith probes with XX bandwidth scopes and
suppose
that we get XX MHz from probe tip to screen? Tain't so.

And the falling HF probe impedance effect is real!

Orin

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of Istvan Novak
Sent: Wednesday, April 01, 2015 6:48 PM
To: waqas chaudhary
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: LVDS 2.5V Vcm(common mode) simulation measurement
correlation

Hi Waqas,
If your signal's rise time is 1ns or 0.8ns, the signal bandwidth is
around
300-400MHz, so if you really have a 500MHz flat transfer profile from
your
probe tips all the way to the scope output, it should be reasonably good
in
this case. Since you say you observed something like a sine wave, it
suggests that somewhere along the way very serious band limitation
occurred.
As Joe said, the 8pF probe capacitance in itself creates a band
limitation
somewhere in the order of 200MHz.

As others pointed out, you can also use a regular volt meter to get the
common mode voltage.
Dont forget to put a 10kohm resistor in series to the signal to isolate
the
input capacitance from your circuit.

Regards,

Istvan Novak
Oracle


On 4/1/2015 9:48 AM, waqas chaudhary wrote:
Hi Istvan,

I am using probe which has 500Mhz bandwidth while my scope has 500MHz
bandwindth and 2GS/s sampling rate. I guess this is too low for 100Mhz
oscillator measurement.

This document from SiTime,
http://www.sitime.com/support2/documents/AN10028-Probing-Oscillator-Ou
tput.pdf

suggests that I need around 1GHz probe with similar scope with atleast
6GS/s if i assume my oscillator rise time is 1ns while it is actually
at max 0.8ns.
I will try to get better scope and probe.

But still i cannot understand the 0.75V Vcm DC level of single ended
lvds signals. It should be 1.25V as fpga vendor says it provides the
Vcm itself in lvds receiver.
I will try changing internal termination schemes to see if it changes
something but at the moment i am using 100 ohm differential.

Or may be i should just remove the AC caps from the clock net to ease
the simulation measurement correlation and let the DC go from the
oscillator to FPGA.

regards
waqas

On Wed, Apr 1, 2015 at 2:36 PM, Istvan Novak <istvan.novak@xxxxxxxxxxx
<mailto:istvan.novak@xxxxxxxxxxx>> wrote:

Hi Waqas,

First you need to make sure that your probe and probe connection
are suitable for the purpose.
Some 10x passive probes may not have more than a couple of hundred
MHz when you use
the best connection, and the bandwidth gets more limited if you
happen to connect the
probe with grip-clips and wires.

Regards,
Istvan Novak
Oracle


On 4/1/2015 3:48 AM, waqas chaudhary wrote:

Hi experts,
I have a board with 100MHz oscillator LVDS 2.5V *AC coupled*
with 100nF
capacitors to clock input pins of FPGA. Clock is working fine
and programs
are running correctly on FPGA using the oscillator clock.

Problem is in simulation and measurement correlation of the
clock net.
In simulation using IBIS models,

oscillator (+) --> 100nf --> FPGA Clkp
oscillator (-) --> 100nF --> FPGA Clkn
| -----
| |
10M 8pF
| |
-------
gnd

10M and 8pF are to include the effect of probe.
I have internal differential termination Rd = 100ohm on FPGA
between Clkp
and Clkn.

*Simulation result* at fpga side of ac coupling cap: *Vcm =
1.25V*

*Measurement result* using 10x passive probe on 500MHz
oscilloscope . *Vcm
= 0.75V*

As i am a beginner,
i) I need some guidance what i am doing wrong in measuring
the clock net
and why there is so much difference in DC level of single
ended (+) and (-)
clock signals.

ii) Also, my measured signal is looking like a pure sinusoid
while
simulation is more like a pulse.

Looking forward to your advice.

Best regards
waqas



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