Lee,
I make it a point of not agreeing with you all the time (humor), but in this
case we concur.
What is often lacking is a systematized approach to high speed design where the
fabrication is validated for all layers, the launch and/or probe locations are
pristinely designed, localized reference planes are clearly established using
causal/passive de-embedding methodology, and loss and material models are
validated (including surface roughness). It is a core design flow thing and
mentality that faces âno time for science experimentsâ hurdles.
Our experience is most EDA simulations that lack benchmark testing are only
achieving 8-15GHz of meaningful sim-measurement correspondence.
- Al
Products for the Signal Integrity Practitioner
Alfred P. Neves
Chief Technologist
Office: 503-679-2429
www.wildrivertech.com <http://www.wildrivertech.com/>
2015 Best In Design&Test Finalist
On Nov 27, 2015, at 5:00 PM, Lee Ritchey <leeritchey@xxxxxxxxxxxxx> wrote:
If you are referring to the capacitance added by a BGA mounting pad you are
off by a decade. Their capacitance is so small it doesn't figure into the
issue. If you are trying to account for the capacitance of the hole barrel
connecting into an internal trace, it is about half what you are using, in
most cases, and can be ignored if your signal travels the length of the via
or barrel. It cannot be ignored if your signal travels only part way down
the via. That is why we sometimes backdrill. This illustrates the problem
we have as an industry. Modeling is done without understanding what the
real circuits look like and incorrect conclusions are drawn from the
results.
Make sure your models look like the real hardware before doing any
simulations if you want results that can be trusted.
Remember, unvalidated simulations are worth the paper they are written
on!!!!
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of shajith Sirajudeen
Sent: Friday, November 27, 2015 2:39 AM
To: amit.j.kumar@xxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Impact of pad cap on return loss
Hi Amit,
You can think about adding series inductance using Tcoil structure to reduce
pad cap effect.
thanks
Shajith
On Fri, Nov 27, 2015 at 4:02 PM, Amit Kumar <amit.j.kumar@xxxxxxxxxxxxx>
wrote:
Hello Experts,
I am designing a package for a 12 Gbps Serdes.
The package layout is showing a differential return loss of about
-13.6dB at 12Ghz(when seen from the package side) in simulations which
looks good to me.
The problem is when I hook up the pad capacitance(400fF on both pads i.e.
padp and padn) on the die side and then look at the return loss(from
the package side) it degrades to -3.5dB at 12GHz.
This is understandable as the impedance of each pad cap at 12 GHz is
around 33 ohms and the effective termination resistance becomes
parallel combination of 50 ohm (termination resistor) and 33 ohms.
The return loss of -3.5dB is a violation of the interface standard I
am working on(OIF-CEI 11.2LR/MR). The spec says the return loss must
be better than -6dB(approx.) at 12 GHz.
Has anyone else seen this kind of problem? Please shed some light on
how this problem can be resolved. Of course one solution can be to
reduce the pad cap. But the question is do we have any alternative way ?
Regards
Amit
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