Hi Amit,
You can think about adding series inductance using Tcoil structure to
reduce pad cap effect.
thanks
Shajith
On Fri, Nov 27, 2015 at 4:02 PM, Amit Kumar <amit.j.kumar@xxxxxxxxxxxxx>
wrote:
Hello Experts,
I am designing a package for a 12 Gbps Serdes.
The package layout is showing a differential return loss of about -13.6dB
at 12Ghz(when seen from the package side) in simulations which looks good
to me.
The problem is when I hook up the pad capacitance(400fF on both pads i.e.
padp and padn) on the die side and then look at the return loss(from the
package side) it degrades to -3.5dB at 12GHz.
This is understandable as the impedance of each pad cap at 12 GHz is
around 33 ohms and the effective termination resistance becomes parallel
combination of 50 ohm (termination resistor) and 33 ohms.
The return loss of -3.5dB is a violation of the interface standard I am
working on(OIF-CEI 11.2LR/MR). The spec says the return loss must be
better than -6dB(approx.) at 12 GHz.
Has anyone else seen this kind of problem? Please shed some light on how
this problem can be resolved. Of course one solution can be to reduce the
pad cap. But the question is do we have any alternative way ?
Regards
Amit
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