[SI-LIST] Re: IBIS question: Test Load for Differential Clock
- From: Bo Yu <yuuboo@xxxxxxxxx>
- To: 델타소년 <imsong91@xxxxxxxxx>
- Date: Tue, 18 Oct 2005 21:27:35 -0700
Hi Song,
Somehow the format of the email messed up. I took your coments below and
put my comments accordingly.
==> In case of common clock distribution system, the major value will be
clock skew betweencpu clock and others, so that the test load will be
cancelled.But I/O signal should be set the correct test load I think.In case
of source sync. clock distribution system, and if the clock and I/O signal
is same type(LVDS, LVTTL...)so that the test load effect will be cancelled.?
[Bo] Sorry, I should mention this is source synchronous system. For example,
Clock and Addr. The Flight Time is measured from Test Load for Addr. My
question is should Clock Flight Time be measured from Test Load as well? Or
we don't care since the timing relation between Clock and Addr may be fixed
by PLL.
B.T.W., Clock and Addr are using different I/O buffer, so the test load
effect will not be 100% cancelled if we DO need to measure the clock from
the Test Load.
=> How about using direct measurement in sigxp making test load in sigxp
windows.?
{Bo] You can do that but it's a separate top file. It can be used to get the
Diff Buffer Delay. How would you apply that Buffer Delay to the current
topology and incorporate it into the Results sheet? I have tens of sweep
simulations so manual calculation is not appropriate.
And use the custom measurement for detecting the crosspoint of differential
signal.?If you can't understand it, pls send me your IBIS model and test
load structure for that differential signals.I will make the .top file for
you.Good Luck! Inmyung Song
[Bo] Could you give me an example of custom measurement for detecting the
crosspoint of diff signal? A simple screen shot would help. Mind you that
the voltage level of crosspoints would vary with different TLine length and
diferent Fast/Typ/Slow corners.
Thanks,
Bo
On 10/18/05, µ¨Å¸¼Ò³â <imsong91@xxxxxxxxx> wrote:
>
>
>
>
> ---------- [ Original Message ] ----------
>
> *Á¦¸ñ:* [SI-LIST] IBIS question: Test Load for Differential Clock
>
> *º¸³½³¯Â¥:* Tue, 18 Oct 2005 17:33:10 -0700
>
> *º¸³½ÀÌ:* Bo Yu <yuuboo@xxxxxxxxx>
>
> *¹Þ´ÂÀÌ:* si-list@xxxxxxxxxxxxx
> Hi folks, I have couple of questions regarding the test load (Cref,
> Rref,...) in an IBIS model for an IO that supplies a clock. (1) Do we care
> if there is a test load for the clock because the timing relationship of
> other signals with respect to that clock (measured at a specific voltage
> level of the waveform) will not change; that is if the clock output-valid
> time is delayed, other signals will also be delayed (keeping the
> timing-relationship the same). Therefore I can always measure clock
> flight-time from driver pin (that is driving full loads) to receiver pin.
> (2) OR, the test load information MUST also be in the clock models (just
> like other signals) and the flight time for the clocks must also be measured
> with respect to the test load.==> In case of common clock distribution
> system, the major value will be clock skew betweencpu clock and others, so
> that the test load will be cancelled.But I/O signal should be set the
> correct test load I think.In case of source sync. clock distribution
> system, and if the clock and I/O signal is same type(LVDS, LVTTL...)so that
> the test load effect will be cancelled.? (3) If you are a Cadence guru, I
> appreciate if you could send me some comments regarding the way SigXplorer
> simulates the diff test load. My experience shows SigXplorer has some
> "limitations" (or may be limitaaation of IBIS to describe the differential
> test load) handling the differential test load. First, the differential
> Buffer Delay (driver driving Test Load) can't be simulated "On the Fly". I
> have to use the "From Library" from Analysis>Preferences. If it's set to "On
> the Fly", you will get warning message and the simulator switches back to
> "From Library". This means you can not display the Test Load waveform and
> receiver waveform in the same scale window and that causes the difficulties
> of Flight Time measurement. Any solution here? Secondly, Model Selector is
> not supported properly. The following is an example of the IBIS model. As
> you can see, the model selector is used. I tried the Buffer Delay
> measurement in the Model Editor from Analysis>Library. I supply the ESPICE
> tset fixture as Test Load, SigXplorer complains model "ddr_o_select" (Model
> Selector instead of real buffer model) is not loaded even though I already
> specified the "ddr_o_yy" in the dialog. Anyone has a workaround here except
> changing the model to not using Model Selector??=> How about using direct
> measurement in sigxp making test load in sigxp windows.?And use the custom
> measurement for detecting the crosspoint of differential signal.?If you
> can't understand it, pls send me your IBIS model and test load structure for
> that differential signals.I will make the .top file for you.Good Luck!
> Inmyung Song.========================================== ....... [Pin]
> signal_name model_name R_pin L_pin C_pin U2 ck# ddr_o_select U3 ck
> ddr_o_select ...... [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min
> tdelay_max |ck ck# U2 U3 0 0 0 0 ...... [Model Selector] ddr_o_select
> ddr_o_xx Use this output only 20 ohm buffer for DDR Address ddr_o_yy Use
> this output only 38 Ohm buffer for DDR Clock ...... [Model] ddr_o_yy
> Model_type Output Vmeas = 900.000mV Cref = 0.000pF Rref = 25.000Ohm.......
> ========================================== Thank you, Bo Yu Intel
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