[SI-LIST] Re: IBIS question: Test Load for Differential Clock
- From: 델타소년 <imsong91@xxxxxxxxx>
- To: <yuuboo@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 19 Oct 2005 12:01:32 +0900
---------- [ Original Message ] ----------
제목: [SI-LIST] IBIS question: Test Load for Differential Clock
보낸날짜: Tue, 18 Oct 2005 17:33:10 -0700
보낸이: Bo Yu <yuuboo@xxxxxxxxx>
받는이: si-list@xxxxxxxxxxxxxxx folks, I have couple of questions regarding
the test load (Cref, Rref,...) in an IBIS model for an IO that supplies a
clock. (1) Do we care if there is a test load for the clock because the
timing relationship of other signals with respect to that clock (measured at
a specific voltage level of the waveform) will not change; that is if the
clock output-valid time is delayed, other signals will also be delayed
(keeping the timing-relationship the same). Therefore I can always measure
clock flight-time from driver pin (that is driving full loads) to receiver
pin. (2) OR, the test load information MUST also be in the clock models
(justlike other signals) and the flight time for the clocks must also be
measured with respect to the test load.==> In case of common clock
distribution system, the major value will be clock skew betweencpu clock and
others, so that the test load will be cancelled.But I/O signal should be set
the correct test load I think.In case of source sync. clock distribution
system, and if the clock and I/O signal is same type(LVDS, LVTTL...)so that
the test load effect will be cancelled.? (3) If you are a Cadence guru, I
appreciate if you could send me some comments regarding the way SigXplorer
simulates the diff test load. My experience shows SigXplorer has some
"limitations" (or may be limitaaation of IBIS to describe the differential
test load) handling the differential test load. First, the differential
Buffer Delay (driver driving Test Load) can't be simulated "On the Fly". I
have to use the "From Library" from Analysis>Preferences. If it's set to "On
the Fly", you will get warning message and the simulator switches back to
"From Library". This means you can not display the Test Load waveform and
receiver waveform in the same scale window and that causes the difficulties
of Flight Time measurement. Any solution here? Secondly, Model Selector is
not supported properly. The following is an example of the IBIS model. As
youcan see, the model selector is used. I tried the Buffer Delay measurement
in the Model Editor from Analysis>Library. I supply the ESPICE tset fixture
as Test Load, SigXplorer complains model "ddr_o_select" (Model Selector
instead of real buffer model) is not loaded even though I already specified
the "ddr_o_yy" in the dialog. Anyone has a workaround here except changing
the model to not using Model Selector??=> How about using direct measurement
in sigxp making test load in sigxp windows.?And use the custom measurement
for detecting the crosspoint of differential signal.?If you can't understand
it, pls send me your IBIS model and test load structure for that
differentialsignals.I will make the .top file for you.Good Luck! Inmyung
Song.========================================== ....... [Pin] signal_name
model_name R_pin L_pin C_pin U2 ck# ddr_o_select U3 ck ddr_o_select ......
[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max |ck ck# U2 U3 0 0
00 ...... [Model Selector] ddr_o_select ddr_o_xx Use this output only 20 ohm
buffer for DDR Address ddr_o_yy Use this output only 38 Ohm buffer for DDR
Clock ...... [Model] ddr_o_yy Model_type Output Vmeas = 900.000mV Cref =
0.000pF Rref = 25.000Ohm ....... ==========================================
Thank you, Bo Yu Intel Corp.
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