[SI-LIST] Re: Frequency criterion in power plane_Power integrity
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: Larry.Smith@xxxxxxx, si-list@xxxxxxxxxxxxx, fangj@xxxxxxxxxxx
- Date: Thu, 9 May 2002 09:46:57 -0700 (PDT)
Jiayuan - There is a big caveat to your statement below. It is true as
long as the current waveform has a rise/fall time greater than 50
nSec. Fifty nSec is forever in terms of a processor clock. It may be
50 or more processor clock cycles. If the power supply voltage seen by
the logic gates is below specification for even 1 clock cycle, bad
things may happen. On the chip, it is desirable to meet target
impedance at a high frequency, probably more than 1 GHz.
Consider a power distribution system that has decoupling capacitance on
the chip, on the package, on the PCB and in the VRM. These are the
circuit nodes where decoupling capacitance is commonly found. The
current from the VRM must flow through the inductance of the VRM
connector, PCB to package interface, and the package to chip
interface. The inductance for each stage of this "power filter" limits
the di/dt that can make it through the inductance without excessive
voltage drop. The di is always constant but the dt depends on where
you look in the circuit.
Suppose a microprocessor takes a 50 amp current step when it comes out
of a sleep state into a full power state. This is likely to happen in
just a few clock cycles. The on-chip capacitance must supply 50 amps
for perhaps 1 nSec (meet target impedance at 350 MHz). After 1 nSec,
the voltage on the chip may have dropped 5% as charge is removed from
the capacitance (Q=CV and I=Cdv/dt). The capacitance on the electronic
package may support the 50 amp current step for 10nSec (meet target
impedance from 35 to 350MHz). The capacitance on PCB might sustain the
current transient for 1000nSec (meet target impedance between 350kHz
and 35MHz). Finally, the VRM may respond to the current transient in
1000 nSec (meet target impedance from DC to 350 kHz).
From this example, it is clear that the frequency where you must meet
target impedance depends greatly on where you are in the power filter.
The example given in a previous email had an excessive amount of
package inductance (50pH) for a system that is going to draw 50 amps at
one volt. The impedance of the PCB node dominates up to 7 MHz. After
that, the inductance of the package begins to dominate. There is
little that can be done at the PCB level to help this system above 7
MHz. Current above that frequency will have to come from the package
or the chip.
regards,
Larry Smith
Sun Microsystems
> From: "Jiayuan Fang" <fangj@xxxxxxxxxxx>
> To: <Larry.Smith@xxxxxxx>, <si-list@xxxxxxxxxxxxx>
> Subject: RE: [SI-LIST] Re: Frequency criterion in power plane_Power integrity
> Date: Wed, 8 May 2002 17:04:57 -0700
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> Larry,
>
> Just want to clarify whether I understand correctly. Do you mean that, as
> long as the power distribution system meets the target impedance up to 7MHz,
> we are guaranteed to have a supply that stays within 50 mV of voltage
> tolerance for 50 amps of current draw?
>
> Regards,
>
> Jiayuan Fang
> SIGRITY, INC.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Larry Smith
> Sent: Wednesday, May 08, 2002 12:46 PM
> To: si-list@xxxxxxxxxxxxx; sghsu55@xxxxxxxxxxxx
> Subject: [SI-LIST] Re: Frequency criterion in power plane_Power
> integrity
>
>
>
> Sogo - the current transition time has a lot to do with inductance and
> current magnitude. The governing equation is V = L*di/dt. Usually, we
> do not want to see more than 5% voltage drop on our power rail and that
> sets V in the above equation. L is a property of the packaging. The
> core power path for a microprocessor might have 50pH loop inductance.
> The current transient might be 50 amps from a 1 V supply. Now that we
> have defined L, di and V, we can calculate the transition time, dt =
> L*di/V = 50pH*50A/.05V=50nSec.
>
> In other words, if we try to draw 50 amps out of a 50pH inductance in
> less than 50 nSec, the voltage is going to droop more than 5% of 1V.
> The GHz frequency associated with a 50nSec rise time is
> 0.35/50nSec=7MHz. This example has been for a microprocessor whose
> core demands lots of current at a low voltage. The fast 50 amp current
> transient simply is not going to make it out of the 50pH package
> inductance.
>
> Let's take another example of a 3.3V memory Dimm that draws 1 amp of
> transient current. Perhaps the equivalent loop inductance for the Dimm
> power supply is 1 nH. By the same calculation, dt =
> 1nH*1A/(3.3*.05)=6nSec. The frequency associated with 6nSec is
> .35/6nSec=57MHz. In other words, the Dimm can draw power from the
> mother board from DC up to 57 MHz. Above that frequency, the power
> will have to come from onboard the Dimm.
>
> Please note that these calculations assume that all current is in the
> Vdd/Gnd loop. If signal return current gets involved, the problem is
> much more complicated. A simple target impedance between Vdd and Gnd
> is a good starting point, but SSN analysis involving Vdd, Gnd and
> signals should be done after that.
>
> regards,
> Larry Smith
> Sun Micorsystems
>
> > From: "sogo" <sghsu55@xxxxxxxxxxxx>
> > To: "'Larry Smith'" <ldsmith@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
> > Subject: RE: [SI-LIST] Frequency criterion in power plane_Power integrity
> > Date: Wed, 8 May 2002 05:36:44 +0800
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> >
> > Hi Larry,
> > I'm pleasure to get your message and appreciate with lots of paper you
> > wrote in this topic. Thank for your detail answer. I'm wonder the
> > frequency band in PC board is so low, only 35MHz. In my project, I would
> > like to simulate the power impedance of PDN in MB. However, the PDN of
> > MB is linked to DDR through DIMM connector. I'm curious that why you
> > define the rise time of PC board only 10ns. If the transient current is
> > from northbridge, I believe the transient time is a couple of ns
> > recently. That is said, the frequency band is about 350MHz. Is it right?
> > In this frequency range, single node modeling of power plane is not
> > sufficient. I have done some simulations, the results indicated the
> > accurate model of power plane is necessary in modern high speed digital
> > system design.
> > Thank for your assistances in advance.
> > Best regards
> >
> > -----Original Message-----
> > From: Larry Smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxx]
> > Sent: Wednesday, May 08, 2002 12:10 AM
> > To: si-list@xxxxxxxxxxxxx; sghsu55@xxxxxxxxxxxx
> > Subject: Re: [SI-LIST] Frequency criterion in power plane_Power
> > integrity
> >
> > Sogo - This is a very important question. By using the target
> > impedance concept in the frequency domain, we can guarantee that a
> > certain voltage tolerance is met in the time domain. But, at how high
> > of frequency must we meet the target impedance? Obviously, we don't
> > have to meet the target impedance at 1 teraHertz.
> >
> > The answer depends upon the rise and fall times of the current
> > transient. The rise time is different at various positions of the
> > circuit. The current transition times at several circuit positions
> > might be as follows:
> >
> > circuit position tRise freq
> > ----------------- ------- ----
> > power connector 1 uSec 350 kHz
> > pc board 10 nSec 35 MHz
> > silicon gates .1 nSec 3.5 GHz
> >
> > The frequency is found by the formula 0.35(GHz)/tRise(nSec). Most of
> > the energy associated with the rising or falling edges is below this
> > frequency. If your power distribution system meets target impedance at
> > the calculated frequency and all the way down to DC at the various
> > points of the circuit, you are guaranteed to have a supply that stays
> > within the voltage tolerance used in the target impedance calculation.
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> > > Delivered-To: si-list@xxxxxxxxxxxxx
> > > X-eGroups-Return: sghsu55@xxxxxxxxxxxx
> > > Date: Mon, 06 May 2002 04:12:53 -0000
> > > From: "sogo_hsu" <sghsu55@xxxxxxxxxxxx>
> > > To: si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Frequency criterion in power plane_Power integrity
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> > >
> > > Hi all,
> > > In high-speed digital system, power integrity becomes an important
> > > issue right now. Some one evaluated power integrity in the quanity of
> > > frequency dependent impedance of power plane, such as target
> > > impedance. As we know, the impedance shall be maintained over a wide
> > > band. But, what's the criterion? Knee frequency ? bandwidth of clock
> > > pulse? or harmonics of clock?
> > > Thanks in advance.
> > > Best regards,
> > > Sogo
> > >
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> >
>
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