[SI-LIST] Re: Frequency criterion in power plane_Power integrity
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx, sghsu55@xxxxxxxxxxxx
- Date: Thu, 9 May 2002 10:24:35 -0700 (PDT)
Sogo - I think we are saying the same thing. A modern microprocessor
in a 50 pH package is in trouble unless there is a lot of decoupling
capacitance on the chip side of that 50 pH package.
If the processor attempts to draw 100 amps through that 50 pH package
(rather than 50 amps), one of two things will happen: 1) the voltage on
the chip side of the 50pH will collapse far enough to satisfy the
V=L*di/dt equation; or 2) the system designer will have put sufficient
decoupling capacitance on the chip side of the 50 pH such that the rise
time of the current through the package is twice as long as it was
before (7MHz goes to 3.5MHz). In each case, V=L*di/dt is satisfied
across the 50 pH package. In the first case, the processor is probably
in trouble because the power supply voltage seen by it's circuits has
dropped substantially. In the second case, charge was supplied by
capacitance closer to the chip and now the corner frequency on the PCB
can be 3.5 MHz because the rise time has been increased. (It also
turns out that the target impedance is half of what it was before.)
Another way to look at this is that the package inductance is the
dominant impedance between the chip and the PCB. You could put a magic
voltage source (zero impedance up to 1 teraHertz) between Vdd and Gnd
at the PCB and it would not deliver much current above 7 MHz. That is
because the impedance (series inductance) of the package is limiting
the current, not the impedance of the PCB. If package inductance
causes the voltage on chip to droop so far that SPEED of the processor
is limited by dirty power, there is nothing a designer can do about it
at the PCB level. The problem has to be fixed at the package or chip
level.
(Please bear in mind that this entire discussion has to do with core
power where only Vdd and Gnd paths are involved. I/O power is an
entirely different problem where we must consider current on signal
traces as well as return current on Vdd and Ground structures (the SSN
problem).)
regards,
Larry Smith
Sun Microsystems
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> From: "sogo_hsu" <sghsu55@xxxxxxxxxxxx>
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> Subject: [SI-LIST] Re: Frequency criterion in power plane_Power integrity
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> Dear Larry,
> I'm glad to get your detailing explanation. However, I do not
> totally agree with your viewpoint. In my opinion, the governing
> criterion in modern digital system is SPEED. In your first example,
> it just simply tell me the microprocessor with 50pH inductance can't
> work properly today. High speed designer have to dwindle the
> effective inductance to meet the timing constraint in Giga operation
> world. In your example, the designer need not to do anything.
> Besides, the simulation and design is very easy due to 7MHz is very
> low frequency. In my opinion, power integrity become a issue is the
> result of rising time decreasing. In addition, in your example, if
> the rated current is double to 100A, then, dt=100nsec, i.e. F=3.5MHz.
> is it resonable?
>
> Best regards,
> Sogo Hsu
>
> --- In si-list@xxxx, Larry Smith <Larry.Smith@xxxx> wrote:
> >
> > Sogo - the current transition time has a lot to do with inductance
> and
> > current magnitude. The governing equation is V = L*di/dt.
> Usually, we
> > do not want to see more than 5% voltage drop on our power rail and
> that
> > sets V in the above equation. L is a property of the packaging.
> The
> > core power path for a microprocessor might have 50pH loop
> inductance.
> > The current transient might be 50 amps from a 1 V supply. Now that
> we
> > have defined L, di and V, we can calculate the transition time, dt =
> > L*di/V = 50pH*50A/.05V=50nSec.
> >
> > In other words, if we try to draw 50 amps out of a 50pH inductance
> in
> > less than 50 nSec, the voltage is going to droop more than 5% of 1V.
> > The GHz frequency associated with a 50nSec rise time is
> > 0.35/50nSec=7MHz. This example has been for a microprocessor whose
> > core demands lots of current at a low voltage. The fast 50 amp
> current
> > transient simply is not going to make it out of the 50pH package
> > inductance.
> >
> > Let's take another example of a 3.3V memory Dimm that draws 1 amp of
> > transient current. Perhaps the equivalent loop inductance for the
> Dimm
> > power supply is 1 nH. By the same calculation, dt =
> > 1nH*1A/(3.3*.05)=6nSec. The frequency associated with 6nSec is
> > .35/6nSec=57MHz. In other words, the Dimm can draw power from the
> > mother board from DC up to 57 MHz. Above that frequency, the power
> > will have to come from onboard the Dimm.
> >
> > Please note that these calculations assume that all current is in
> the
> > Vdd/Gnd loop. If signal return current gets involved, the problem
> is
> > much more complicated. A simple target impedance between Vdd and
> Gnd
> > is a good starting point, but SSN analysis involving Vdd, Gnd and
> > signals should be done after that.
> >
> > regards,
> > Larry Smith
> > Sun Micorsystems
> >
> > > From: "sogo" <sghsu55@xxxx>
> > > To: "'Larry Smith'" <ldsmith@xxxx>, <si-list@xxxx>
> > > Subject: RE: [SI-LIST] Frequency criterion in power plane_Power
> integrity
> > > Date: Wed, 8 May 2002 05:36:44 +0800
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> > >
> > > Hi Larry,
> > > I'm pleasure to get your message and appreciate with lots of
> paper you
> > > wrote in this topic. Thank for your detail answer. I'm wonder the
> > > frequency band in PC board is so low, only 35MHz. In my project,
> I would
> > > like to simulate the power impedance of PDN in MB. However, the
> PDN of
> > > MB is linked to DDR through DIMM connector. I'm curious that why
> you
> > > define the rise time of PC board only 10ns. If the transient
> current is
> > > from northbridge, I believe the transient time is a couple of ns
> > > recently. That is said, the frequency band is about 350MHz. Is it
> right?
> > > In this frequency range, single node modeling of power plane is
> not
> > > sufficient. I have done some simulations, the results indicated
> the
> > > accurate model of power plane is necessary in modern high speed
> digital
> > > system design.
> > > Thank for your assistances in advance.
> > > Best regards
> > >
>
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