[SI-LIST] Re: Frequency criterion in power plane_Power integrity
- From: "gurunath vinayakrao kulkarni" <gurunath.kulkarni@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 17 May 2002 09:04:41 +0530
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----- Original Message -----
From: "Chris Cheng" <chris.cheng@xxxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Friday, May 17, 2002 5:49 AM
Subject: [SI-LIST] Re: Frequency criterion in power plane_Power integrity
>
> The best "decoupling" is to reference your DDR signals between
> the vterm(1.25V) plane and ground. The tight coupling provide
> the lowest possible impedance path between the signals and
> the return path to vterm. The pair vterm and gnd plane that
> sandwich the signals also provide the initial decoupling
> for the vterm. You take care of the return current to
> driver power through on-die decoupling. Unless you are
> prepared to simulate the whole loop between the driver,
> signal trace, planes, via, rterm pads, you will not be able
> to undertand the level of decoupling you need. This is
> not a simple power impedance analysis between power
> source and driver.
> The switching rate of the vrm depends on what you use
> but that is a bulk decoupling issue where you can use
> the simple formula of
> I*t=C*dv where I is the peak current (probably with
> activity derating), t is the supply switching time
> C is the total cap you need, dv is the voltage
> drop you can live with. I would use .01uf,.1uf or 1uf for
> the quantity of capacitance you can calculate based
> on the formula. Anything with capacitance smaller
> than .01uf will be a waste of money on a regular
> PCB.
> When all is said and done, still don't need to
> simulate. Don't waste your time (unless you are
> prepared to build the above mentioned model).
>
> Chris
>
>
>
> -----Original Message-----
> From: sogo_hsu [mailto:sghsu55@xxxxxxxxxxxx]
> Sent: Thursday, May 16, 2002 3:49 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Frequency criterion in power plane_Power integr
> ity
>
>
>
> Chris,
>
> Thank you for your advise. Yes, I agree with you totally. Could you
> tell me what's the switching rate in last case? about 1ns or 1us?
> Thank you in advance.
> Best regards,
> Sogo
>
> --- In si-list@xxxx, Chris Cheng <chris.cheng@xxxx> wrote:
> >
> > If you are dealing with DDR. The power distribution is not
> > as simple as you think.
> > The I/O current actually flows between the driver (which is
> > usually powered by the 2.5V VRM) and the terminator (which
> > is usually powered by a seperate 1.25V VRM). The switching
> > current can only return through tight coupling between
> > the signals and its gnd reference plane and decoupling between
> > ground and the terminators.
> > Don't waste your time trying to simulate the power
> > impedance between the VRM and CPU/chipset. Thats not the
> > current loop for the highspeed DDR I/O.
> > Chris
> >
> > -----Original Message-----
> > From: sogo_hsu [mailto:sghsu55@xxxx]
> > Sent: Thursday, May 16, 2002 9:17 AM
> > To: si-list@xxxx
> > Subject: [SI-LIST] Re: Frequency criterion in power plane_Power
> > integrity
> >
> >
> >
> > Larry,
> > Manu thanks for your kind answer. I agree with your viewpoint.
> > However, my keypoint is how to evaluate the sufficience of
> decoupling
> > capacitor and performance of PDS in frequency domain. Also, I would
> > like to build up a model to simulate and/or estimate voltage droop
> in
> > equivalent circuit. As you posted in the message discussed with
> > Zhiping, the design of PDS is a system level issue. Let us consider
> a
> > case as
> >
> > VCCP---VRM linear model--decaps--uP----connector----DDR(133MHz)
> >
> > In this case, what's the frequency criterion in PDS design? My
> boss
> > will ask me, may we reduce some decaps to dwindle cost but still
> meet
> > the voltage specification? My customer will ask me, may the PCB
> > support 266MHz DDR? In my opinion, the rise time shall be set as
> > about 1ns to meet the requirement of DDR data switching. Therefore,
> > the impedance of whole PDS, including plane, has to meet target
> > impedance constraint up to about 500Mhz, the knee frequency of 1ns
> > rising time, to avoid extreme dirty power.
> >
> > Thank you very much in advance.
> > Best regards,
> > Sogo
> >
> >
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