[SI-LIST] Free Signal Integrity Analysis Workshops in September from ANSYS
- From: Margaret Schmitt <margaret.schmitt@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 2 Sep 2014 09:09:23 -0700
Hi All,
ANSYS will host free "Lunch & Learn" workshops on Signal Integrity Analysis
at their San Jose & Irvine office locations in September.
The workshops will provide attendees hands-on experience in computing eye
diagrams using statistical transient circuit analysis and creating
automated DDR3 pass/fail compliance reports for a PCB design. These
workshops are recommended for anyone implementing high-speed interfaces
like DDR3 in their designs.
The workshops are free of charge, and a detailed agenda & registration
links are available on the following sites, for each location:
*San Jose, CA: *Thursday, September 25, 11:30am - 1:30pm
http://ansys.com/About+ANSYS/Events/Signal+Integrity+Analysis+Using+ANSYS+SIwave-sanjose-9-25-14
*Irvine, CA: *Friday, September 26, 11:30am - 1:30pm
http://ansys.com/About+ANSYS/Events/Signal+Integrity+Analysis+Using+ANSYS+SIwave-irvine-9-26-14
Kind Regards,
-Margaret
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