[SI-LIST] Re: Flight Time
- From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
- To: "'whizplayer@xxxxxxxxx'" <whizplayer@xxxxxxxxx>,si_list <si-list@xxxxxxxxxxxxx>
- Date: Wed, 13 Nov 2002 17:47:56 -0800
Hi Bob,
Its not always the case that signal and clock should be equal length for
best margins, but its a reasonable place to start. This is the case when
clock and data or strobe and data are identical in topology and loading,
assuming the data valid to strobe and data valid after strobe specs are
fairly symetrical. In other cases you really have to solve the timing
margins for setup and hold using all four flight corners, clk-min, clk-max,
data-min, data-max, and then equalize your setup and hold margins. The
differences in loading and topology can create offsets between optimal clock
length and optimal data length. You are correct of course that any positive
margin can be traded off for length mismatch once centered.
Also, I don't always use skew as a metric. Sometimes I use skew and
sometimes I use flight time, depending on how the margin formulas are
written, and the characteristics of the two signals in question. We tend to
use skew based formulas for closely matched source synchronous busses where
data and strobe have identical buffers and toplogies and your just looking
for interconnect and buffer induced skew. In this case skew is a tightly
controlled metric which correaltes to bus performance limits. In other cases
such as clock to address or clock to control where topologies and loading
differences create very large differences in flights we just go with flight
time based analysis, since skew isn't a meaningful metric.
Brian P. Moran
Signal Integrity Engineer
Intel Corporation
brian.p.moran@xxxxxxxxx
-----Original Message-----
From: Bob Patel [mailto:whizplayer@xxxxxxxxx]
Sent: Wednesday, November 13, 2002 2:57 PM
To: si_list
Subject: [SI-LIST] Flight Time
Hi! I had a question regarding Flight time. If I
calculate the maximum flight time to meet the setup
time and minimum flight time to meet hold time ans say
they are maxFlt time=4ns and min Flt time=1.28ns.
This is for a source synchronous bus, then what should
I keep the trace length for clock & parallel 15 bit
data bus.
I am saying I can keep the clock bus around the same
length and the length between the min & max flight
times.
Do you'l see any problems?
THanks
Bob
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