Scott,
Let me reassure you that my intuition is not drawing me to conclusions in
contrary to neither Istvan Novak nor Larry Smith. In fact, my intuition isn't
really telling me anything useful here which is why I'm trying to figure out
how I can analyze the problem properly.
Regards,
Martin
From: Scott McMorrow <Scott@xxxxxxxxxxxxx>
To: "istvan.novak@xxxxxxxxxxx" <istvan.novak@xxxxxxxxxxx>; Martom Last
<yahbalo@xxxxxxxxx>; "larry.smith@xxxxxxxxxxxxxxxxxxxxx"
<larry.smith@xxxxxxxxxxxxxxxxxxxxx>; "si-list@xxxxxxxxxxxxx"
<si-list@xxxxxxxxxxxxx>; "steve@xxxxxxxxxxxx" <steve@xxxxxxxxxxxx>
Sent: Wednesday, May 17, 2017 1:43 AM
Subject: [SI-LIST] Re: First-order modelling of parallel-plate capacitance
Martam
If your intuition seems to draw you to different conclusions than Istvan Novak,
or Larry Smith, I'd advise you to question your intuition, and either believe
the experts, or do the work to confirm their results. These two will never
steer you wrong, in my experience.
Scott McMorrow, CTO Signal Integrity Group
Samtec
Office 401-284-1827 | +1-800-726-8329
www.samtec.com
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Istvan Novak
Sent: Tuesday, May 16, 2017 7:29 PM
To: Martom Last <yahbalo@xxxxxxxxx>; larry.smith@xxxxxxxxxxxxxxxxxxxxx;
si-list@xxxxxxxxxxxxx; steve@xxxxxxxxxxxx
Subject: [SI-LIST] Re: First-order modelling of parallel-plate capacitance
Martom,
Based on a lot of measurements and simulations, my conclusion is that the
uniform assumption yields probably the lowest inductance.
BTW big or small are relative terms. When it comes to inductance, the
33pH/mil inductance is not big: if you try to measure it, it proves to be quite
challenging.
Regards,
Istvan Novak
Oracle
On 5/16/2017 6:26 PM, Martom Last wrote:
Istvan,
I don't know what I expected, but the stated approximate sheet
inductance value of 33pH per mil of separation distance (or 1.3 pH per
micrometer) is surprisingly high--at least compared to zero! I note
that the derivation of this rule of thumb [1] assumes uniform current
flow across the square. But, if I'm not mistaken, uniform current flow
in turn implies uniform inductance (current follows the path of least
impedance), making the reasoning look somewhat circular to me. Maybe
I'm not thinking straight here, but I struggle a bit to wrap my head
around it completely. It is also not clear to me how the uniform
current flow assumption holds up as the frequency goes up--my
understanding is that current flows in increasingly confined paths of
low inductance loops which, to my mind, is the opposite of uniform
current flow. Isn't this problematic when it is precisely at high
frequencies this plane capacitance is supposed to be beneficial.
Larry,
In my particular case, there is no on-die capacitance that I know of.
My newly added plane inductance did, however, stick out like a sore
thumb in my (Spice) model when seen side-by-side with the discrete
capacitors. As a side-note, my usual modelling strategy with the
discrete 0402 caps is to plug in the via parameters into Saturn PCB
Design tool and adjust via height to match the distance to the nearest
plane (ignoring the stub), and then plug this inductance value into
Spice as an additional ESL to whatever is in the capacitor model from
the vendor. I get ESL values near what you mention (500pH) so I hope
the method I use is not too bad.
Apart from that, I'm still trying to come to terms with your post
which was clearly a bit too much to process for my
sleep-deprived-father-of-a-two-year-old mind. Having ready your post
multiple times, I'm still reading it as an advocate for loosely
coupled PWR-GND planes, and that we'd be better off without plane
capacitance altogether because a) discrete caps offer a lower total
ESL which is trumped (sorry) by the plane inductance, and b) the
too-low-to-be-of-any-use plane capacitance is still large enough to
form a resonating tank at frequencies where we don't want them.
In the paper Istvan linked to, there was a section about the impact of
increased plane size on resonance suppression. How does that play with
what you are saying here?
Steven,
I'll come back to your comment about the shortcomings of Spice at a
later time. I want to sort out the fundamentals first.
[1]
http://www.edn.com/electronics-blogs/all-aboard-/4434907/Sheet-inducta
nce-of-a-cavity--Rule-of-Thumb--16
Regards,
Martin
On Tuesday, May 16, 2017 8:19 PM, Larry Smith
<larry.smith@xxxxxxxxxxxxxxxxxxxxx> wrote:
Martin â Istvan has given you a good rule of thumb for the sheet
inductance of PCB power planes. It is 33 pH per square for 1 mil
thick dielectric, double that for 2 mil dielectric. Inductance is the
most important PDN property for the board power planes. As you
mention, we might get 400 pF per square inch power plane capacitance.
But in most cases, the board power plane capacitance pales in
comparison to on-die capacitance which is likely to be 10âs or even
100âs of nF. With the on-die capacitance being much more than the
board power plane capacitance, you can see why the most important
property of the of the power planes is inductance.
The main function of the board power planes (at least for power
integrity concerns) is to bring current (charge) stored in board
capacitors to the die load. Well mounted board capacitors may have 500
pH of inductance. If we put 10 caps in parallel, the effective
mounted inductance is 50 pH. Note that this is less than the expected
66 pH per square of 2 mil dielectric power planes. If we use just one
square of PCB power plane to hook up 10 caps, the dominant inductance
is in the power planes. Additional caps only provide marginal PDN
improvement when the dominant inductance is in the plane.
One additional relevant comment is that the board power plane
capacitance forms a parallel resonant peak with inductance of all the
mounted board caps. This is an LC resonance that is almost always
lower frequency than any board cavity resonances that are associated
with the dimensions of the power planes. For power integrity purposes,
this is the resonant peak to watch out for. It is best to minimize
the power plane area, which minimizes the board capacitance and moves
this LC resonant peak up to a higher frequency. We want the board LC
resonance to be at a higher frequency than the resonant peak between
the on-die capacitance and inductance to board caps.
In other words, the capacitance from the board power planes is more of
a problem for us than it is a benefit.
regards,
Larry Smith
________________________________
From: si-list-bounce@xxxxxxxxxxxxx
<mailto:si-list-bounce@xxxxxxxxxxxxx> <si-list-bounce@xxxxxxxxxxxxx
<mailto:si-list-bounce@xxxxxxxxxxxxx>> on behalf of Istvan Novak
<istvan.novak@xxxxxxxxxxx <mailto:istvan.novak@xxxxxxxxxxx>>
Sent: Sunday, May 14, 2017 3:43 PM
To: dmarc-noreply@xxxxxxxxxxxxx <mailto:dmarc-noreply@xxxxxxxxxxxxx>;
si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Re: First-order modelling of parallel-plate
capacitance
Hi Martin,
In short, if we ignore the modal resonances for a second, you have
static plane capacitance and the separation-related inductance, which
forms a V-shape impedance profile, similar to that of capacitors. The
inductance of the planes is frequency, shape and location dependent,
but for a quick guide you can use the approximate sheet inductance,
which is 33pH for each miliinch of separation. At high frequencies
(which is a relative term) you are likely beyond the first series
resonance of the planes, so the impedance is dominated by the
inductive reactance, which in turn is dependent only on the plane
separation and independent of the static capacitance.
You can find a lot of free material posted on the web on this subject,
see for instance
http://www.electrical-integrity.com/Paper_download_files/DC08_Modal_Su
ppress_SUN.pdf
Regards,
Istvan Novak
Oracle
On 5/14/2017 2:24 PM, Martom Last (Redacted sender yahbalo for DMARC)
wrote:
Hicapacitor with area A and plate separation distance d is a better
I'm trying to understand why, for a given laminate, a parallel plate
high-frequency charge reservoir than a parallel plate capacitor with
area 2A and separation distance 2d.
On page 10 in [1], Lee Ritchey states thatplaced closer together two things happen.ÃÂ First, the capacitance
"Planes in parallel naturally form a capacitor. As the planes are
between them increases and, second, their inductance decreases. When
the planes are separated by 2-3 mils (51-76 microns) the capacitance
approaches 400 pF per square inch (6.5 pF square cm) and the
inductance becomes very low compared to that of discrete capacitors (a
few picoHenries). It is this very low inductance that makes this
capacitor function well into the hundreds of megahertz."
My guess here is that since a tightly coupled plane pair holds morecharge per area than a loosely coupled plane pair, the current loop
related to charge transfer to and from the plane pair, and hence the
inductance, is less in the tightly coupled case where more local
charge is available. Is this understanding correct?
separation distance and the series inductance of the resulting
What is the mathematical relationship between the inter-plane
capacitance?
capacitor, the value of which I base on a simple ideal parallel plate
Also, when I model my PDN in Spice I usually add an ideal "plane"
capacitor with area equal to the board/plane area. However, this
approach does not seem to take into account the finite propagation
velocity in a typical FR4 type laminate, and I'm now thinking that
this ideal capacitor representation of my plane capacitance (as seen
by a fast switching IC) should be reduced to only include the parallel
plate disk with radius r=v*t, where v is the propagation velocity and
t is the time it takes to move charge. Charge outside this disk would
take longer than the rise time of the signal and be invisible. Does
this make sense?
[1] Designing a Power Delivery Subsystem (2011, Lee Ritchey)with 'unsubscribe' in the Subject field
Regards,
Martin
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