Hi Chetan,
I assume you are looking for a design process, as opposed to analyzing
an existing design.
You need of course simulated or measured data for the other components
as well: capacitors and the DC source.
Whether you can stop with the impedance or need to proceed to
time-domain analysis, depends on how you obtained your design target.
If you came up with (or someone gave you) a proper impedance target
(emphasis is on 'proper'), you can stop at comparing impedances.
If your design target was given in the time domain, you need to continue
to figure out the time-domain noise, but this requires some good
knowledge or decent assumption about the current signature hitting the PDN.
Regards,
Istvan Novak
Oracle
On 5/22/2017 1:56 PM, chetan reddy wrote:
Hi All,
i have few question in Decoupling analysis:
The way i am doing Decoupling analysis is "extracting S parameters from the
board for a rail and cascading it with the package S parameters and on die
cap and checking the impedance profile( by plotting Z parameters).
Is it enough or do we need to run the time domain simulations and ensure it
again?
Kindly provide me the process flow various engineers follow.
Regards
Chetan
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