Hi
I'm trying to understand why, for a given laminate, a parallel plate capacitor
with area A and plate separation distance d is a better high-frequency charge
reservoir than a parallel plate capacitor with area 2A and separation distance
2d.
On page 10 in [1], Lee Ritchey states that
"Planes in parallel naturally form a capacitor. As the planes are placed closer
together two things happen. First, the capacitance between them increases
and, second, their inductance decreases. When the planes are separated by 2-3
mils (51-76 microns) the capacitance approaches 400 pF per square inch (6.5 pF
square cm) and the inductance becomes very low compared to that of discrete
capacitors (a few picoHenries). It is this very low inductance that makes this
capacitor function well into the hundreds of megahertz."
My guess here is that since a tightly coupled plane pair holds more charge per
area than a loosely coupled plane pair, the current loop related to charge
transfer to and from the plane pair, and hence the inductance, is less in the
tightly coupled case where more local charge is available. Is this
understanding correct?
What is the mathematical relationship between the inter-plane separation
distance and the series inductance of the resulting capacitance?
Also, when I model my PDN in Spice I usually add an ideal "plane" capacitor,
the value of which I base on a simple ideal parallel plate capacitor with area
equal to the board/plane area. However, this approach does not seem to take
into account the finite propagation velocity in a typical FR4 type laminate,
and I'm now thinking that this ideal capacitor representation of my plane
capacitance (as seen by a fast switching IC) should be reduced to only include
the parallel plate disk with radius r=v*t, where v is the propagation velocity
and t is the time it takes to move charge. Charge outside this disk would take
longer than the rise time of the signal and be invisible. Does this make sense?
[1] Designing a Power Delivery Subsystem (2011, Lee Ritchey)
Regards,
Martin
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