[SI-LIST] Re: Eye width for microstrip and stripline configuration in PCIE gen2 simulation.

  • From: "Alfred P. Neves" <al@xxxxxxxxxxxxxxxxx>
  • To: si-list <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 21 Feb 2013 10:13:50 -0800

When we compare eye diagrams in either 3D EM simulation or measurement (VNA or 
differential TDR) in addition to simple loss, SDD21, we analyze:

1.   simple pulse response, rise time response, ringing, reflections, etc.,
2.   SDD11, differential return loss
3.   group delay variation of SDD21

If your input PRBS or NRZ data signal is not a clean gaussian pulse response, 
but is a ragged PWL sampled system, your eye will appear worse with the wider 
bandwidth system.

Run a clock pattern with the same rise times, that is 1/5 the data rate and 
compare the simulation results is another suggestion.








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Alfred P. Neves
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On Feb 21, 2013, at 10:00 AM, Joseph.Schachner@xxxxxxxxxxxxxxxxxx wrote:

> microstrip, because it is not sandwiched between ground planes, is more 
> susceptible to crosstalk than stripline. Cross talk might be the cause of 
> more eye closure with microstrip. 
> Another likely cause is that with microstrip the electromagnetic field 
> exists both above the microstrip (in the air) and below it (in the 
> substrate).  That non-homogeneous medium makes the dielectric constant 
> vary with frequency which means it is dispersive - the phase velocity 
> decreases with increasing frequency. That pulls fast edges apart.   And, 
> the characteristic impedance changes with frequency ... I don't remember 
> exactly how to describe that.  These effects can be small depending on 
> usage, but one thing is certain: they will contribute to eye closure for 
> microstrip and they basically do not exist for stripline.
> 
> Insertion loss is not the only thing that needs to be considered.
> 
> --- Joe S.
> 
> 
> 
> From:   Siddharth Rajagopalan <maxsidhu@xxxxxxxxx>
> To:     si-list@xxxxxxxxxxxxx, "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
> Date:   02/21/2013 11:24 AM
> Subject:        [SI-LIST] Eye width for microstrip and stripline 
> configuration in PCIE gen2 simulation.
> Sent by:        si-list-bounce@xxxxxxxxxxxxx
> 
> 
> 
> Dear experts,
> I am currently working on a PCIE gen2 simulation. I am evaluating both the
> microstrip and the stripline configurations.As expected, the stripline
> configuration yields more insertion loss than the microstip one. This
> however is not reflected in the eye diagram since the stripline has a
> better eye width than the microstrip one. I was of the understanding that
> higher insertion loss manifests itself as higher rise time degradation in
> the time domain. I might exposing my ignorance in the previous statement.
> kindly help me clarify this.
> Thanks,
> siddharth rajagopalan
> 
> 
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