[SI-LIST] Re: Effect of dielectric spacing between power and ground

  • From: "Wilson, Ralph A, III (Ralph)" <ralph.wilson@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 23 Jun 2016 19:51:34 -0500

C = eA/h, where "e" is epsilon (er x e0), A the area of the overlapping 
plates, and h
the separation distance.  Simple plate capacitor.

Ralph

On 6/23/2016 5:58 PM, Curt McNamara wrote:

We are looking at a board stack up with 10 mil spacing between the center
layers (which are power and ground). It is a 10 layer pcb with continuous
ground planes adjacent to high speed signals. There is ample space for
decoupling.
How can i estimate the effect of reducing the spacing between power and
ground?

Thanks in advance.

      Curt


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