Hi Stephen,
If you see the need for IBIS specs enhancements why don't you rise those
questions on the IBIS committee meetings instead of taking advantage of this
forum for free advertising of your solutions?
Cristian
On Oct 25, 2017, at 9:40 PM, "slater@xxxxxxxxxxxx" <slater@xxxxxxxxxxxx>------------------------------------------------------------------
wrote:
Hi Arpad,
I do certainly believe in the founding principles of IBIS, and agree that it
benefits the entire community to pull together under standard modeling
constructs. I should clear up that I mean only that there is no need to
complicate the *IBIS-AMI* part of the standard at present. I do see a need
for an additional external EQ file (encrypted) to be shared with IBIS files.
The encryption is not for the purpose of making it proprietary to the EDA
vendor, but for the purpose of protecting IP. I see no issue to raise a
BIRD with the IBIS committee in the future.
Message me personally if you'd like to connect on this topic.
Best regards,
Stephen.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Muranyi, Arpad
Sent: Wednesday, October 25, 2017 8:08 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Stephen,
The technical part was OK and appreciated.
The offending part was your discussion of Keysight's solutions and its
capabilities, practically inviting people to turn to Keysight for support.
The worst of this was your conclusion that there is no need to add anything
to IBIS because you offer a (most likely proprietary) solution for these
needs. Mentor, and probably other vendors could also offer similar or
equivalent solutions and would love to encourage everyone to come to us
because we are eager to provide our expertise and support.
Obviously there is no need for a spec or standard if everyone would just use
"MY" product(s) to do all their work... But IBIS is there despite all of its
shortcomings because it promises portability, interoperability, tool
independence, etc... so that different IC and tool vendors and system
designers could all work together.
Arpad
=======================================================
-----Original Message-----
From: slater@xxxxxxxxxxxx [mailto:slater@xxxxxxxxxxxx]
Sent: Wednesday, October 25, 2017 9:38 PM
To: Muranyi, Arpad <Arpad_Muranyi@xxxxxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: RE: EQ for DDR5
Arpad, I was careful to include technical solution details for a problem that
many of our mutual customers are asking. My aim was to further the
discussion on whether or not IBIS-AMI is suitable for DDR or not. It is a
topic that many SI-listers do have an interest in. My aim was to be
educational, and to settle any fears that our EDA community doesn't have
working approaches to these problems.
If all deem my opinion here to be unworthy of pushing forward the
conversation, then for that I am truly sorry.
Best Regards,
Stephen.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Muranyi, Arpad
Sent: Wednesday, October 25, 2017 4:54 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Stephen,
This forum should not be used for blatant product advertisements!!!
You are not the only one who has proprietary solutions for this type of
simulations.
Arpad
======================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of slater@xxxxxxxxxxxx
Sent: Wednesday, October 25, 2017 6:19 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] EQ for DDR5
Dear SI-Listers,
I wanted to pick up an earlier thread from Nathan, Nitin and Walter regarding
how best to simulate EQ in the upcoming DDR5 interfaces (and the highest
speed grade of DDR4 @3200MT/s). Indeed this has been a recurring topic of
conversation, between chip vendors, system designers and EDA vendors. There
have been multiple papers at DesignCon 2016 and 2017 presenting analyses of
EQ applied to DDR.
Here's a link to a DesignCon paper demonstrating the application of CTLE,
co-authored with a partner:
https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.xilinx.com%2Fpublications%2Fevents%2Fdesigncon%2F2017%2Fcharacterization-ddr4-receiver-sensitivity-impact-post-equalization-eye-paper.pdf&data=02%7C01%7C%7Cce2034fe09a34e8d0b1108d51c03c4ad%7C63545f2732324d74a44dcdd457063402%7C1%7C1%7C636445724876252401&sdata=1g2rgyHdxFGDv7FysP%2BsVSYPWskAZLwXa%2Byv3CQdmRE%3D&reserved=0
Walter's article pointed out that IBIS-AMI is designed for differential
signaling and is not presently suited to tackle single-ended DDR interfaces.
He also quite correctly pointed out that the eye in the single-ended DQ and
CA signals is asymmetric, meaning the rising edges and falling edges are very
different. To the casual reader it may seem that EDA vendors don't have a
working solution for this today. However this is not the case, as Keysight
has had a solution for DDR with EQ since 2014.
The technical solution is a DDR Bus Sim (a statistical channel simulation
that characterizes both rising and falling edges independently). Here the
IBIS model is characterized as part of the channel, and the thankfully the EQ
that is being proposed for DDR5 can be modeled very well statistically, such
as CTLE and DFE. These Rx settings are part of the normal simulation setup.
The ultimate aim is to present the equalized eye and the BER contours in
order to make measurements of margin to the Rx BER Mask.
If you're a HW engineer (not a chip designer), then my recommendation would
be to partner up with your DRAM vendor and Memory Controller vendor to best
start your simulation of these designs. Keysight is always there to provide
support, and can encrypt the EQ settings to protect the chip vendors' IP.
We don't see a need to add complexity to the IBIS-AMI standard at this point
in time. I hope this adds an alternative perspective to the discussion.
Best regards,
Stephen Slater
Product Manager for High Speed Digital Design Keysight EEsof EDA Division
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