Why do you think equalization can only be done by statistical analysis in DDR ?
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: Bhagwath, Nitin [mailto:Nitin_Bhagwath@xxxxxxxxxx] ;
Sent: Friday, October 27, 2017 5:30 PM
To: Cheng, Chris <chris.cheng@xxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: EQ for DDR5
We need to separate the need for statistical analysis from the need for
equalization analysis. Both have been used for Serial links with IBIS-AMI, but
DDR5 really only needs support for DFE. If this involves requiring IBIS-AMI,
well, that's the fun conversation in the IBIS-AMI committee to make sure that
SSO, DQS, non-asymmetric and other limitations are worked around. An
industry-standard support is still a work-in-progress.
If you're talking only about being able to do SSO and incorporate DQS, well,
many tools support that today (including HyperLynx). Simply do a time-domain
simulation with a few thousand bits. The ringing should die down within a
couple of round-trips.
There's the answer. What's the question again?
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Cheng, Chris
Sent: Friday, October 27, 2017 5:00 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Single end source synchronous bus like DDR is very difficult to do statistical
analysis.
Single ended driver with active termination is most likely non-LTI. SSO is a
worst case analysis with odd and even mode SSO impact. Also, strobe placement
is different between read and write so SSO impact is different between the two
conditions. While protocol guarantee only 50% bus switching, nearby bit
switching will saturate the SSO impact within a few local bits. You always
simulate only the worst case impact because you're like to run into it in real
life.
DDR bus is very different from serial bus. The burst is mostly limit to 4x, 8x
bit for random cache line access. Deep BER analysis is really meaningless in
real life. Just pretty pictures.
However, protocol corner cases like strobe pre/postamble timing analysis is
important also. Leveling training is notoriously problematic.
Anyone who claim there is a package for DDR bus analysis better have answers to
the above.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx<mailto:chris.cheng@xxxxxxx> / Email
4209 Technology Dr
Fremont, CA 94538
USA
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