[SI-LIST] Re: EQ for DDR5
- From: Scott McMorrow <Scott@xxxxxxxxxxxxx>
- To: "nitin_bhagwath@xxxxxxxxxx" <nitin_bhagwath@xxxxxxxxxx>, "chris.cheng@xxxxxxx" <chris.cheng@xxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>, "slater@xxxxxxxxxxxx" <slater@xxxxxxxxxxxx>
- Date: Sat, 28 Oct 2017 13:23:43 +0000
I'll just throw this out there.
I'm in Chris Cheng's camp. Channel and SSO power simulations can only be
separated in the manner you describe if, and only if, they are linearly
independent. That is not always the case. Single ended systems horribly fail in
that regard.
Your assumption is that noise in the power/ driver system linearly modulates
signaling. Throw a few resonance in and that assumption is broken. Throw in
mixed referencing and that assumption is broken. Throw in a poorly localized
package with coupling between power and signals and that assumption is broken.
Feedback and feed forward between the power systems and the signaling systems
break LTI assumptions. Multiple simultaneous channels operating in opposite
directions often break LTI assumptions. Single ended drivers and receivers are
much more strongly non-LTI than differential SERDES. Coupling into the power
system often presents itself is apparent (not real) causality violations.
Pigs can sometimes fly ... but it ain't pretty.
I've been involved in the design of 100s of memory systems in my career. Our
team at Samtec has many more under their belt. I'm not being hyperbolic in
saying that I find designing a 112G PAM4 channel easier than DDR.
DDR5 scares me.
Comments?
Get Outlook for Android<https://aka.ms/ghei36>
________________________________
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx> on behalf of
slater@xxxxxxxxxxxx <slater@xxxxxxxxxxxx>
Sent: Saturday, October 28, 2017 4:34:38 AM
To: Nitin_Bhagwath@xxxxxxxxxx; chris.cheng@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Hi Chris,
I'll chime in again. DFE does not easily have a representation in Transient
(i.e. SPICE) simulation, since the DFE is applied after the latch.
If you had the full transistor level circuitry for the EQ you could simulate it
with a transient solver, but that is not what is available to a system
designer. It would also be much slower to simulate the full SPICE level
circuitry than any IBIS (or IBIS-AMI) model representation of the same.
The EQ can be more easily applied in statistical because mathematically you can
calculate what the impact of the CTLE and DFE will be on the impulse responses
(one for rising, one for falling) and compute the final eye.
The point Nitin makes about when statistical analysis becomes important really
has to do with the worst case bit pattern. At lower speed grades you could
simulate a few thousand bits and feel comfortable you've captured the worst
case bit pattern. As the data rate increases, the number of bits 'in flight'
in the channel increases (the channel is electrically longer, and reflections
affect many future bits). To make things worse, the same is true for every
neighboring line, which means crosstalk also has impact on many future bits.
The number of possible permutations for bit patterns increases exponentially;
One of which is the worst case.
At DDR4 and DDR5 rates, the BER is specified... and it is very low (1e-16).
Statistical channel simulations calculate down to this level very quickly. It
always captures the worst case eye closure. That is the point of using it
(well that and the case that statistical sim is fast).
However you also mentions SSO... that is a time-varying affect.. It can only
be captured by a transient simulation. In that respect transient and
statistical channel simulation are very much complementary. Our
recommendation is that since the SSO is a deterministic jitter, simulate with
transient with an ideal power supply, then simulate with the real PDN, and note
the change in amplitude noise, and jitter. You only need a few thousand bits
to capture the spread of this effect.
That change needs to be fed into the channel simulation either as a Dj
variable, or by simply increasing the Rx BER mask by the same amounts,
effectively giving yourself less margin. There's a DesignCon 2017 paper on this
topic and it correlates well to measurement.
I hope this helps.
Best regards,
Stephen.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Bhagwath, Nitin
Sent: Friday, October 27, 2017 6:51 PM
To: chris.cheng@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Why do you think equalization can only be done by statistical analysis in
DDR ?
I don't.
As in my first sentence, we need to separate equalization from statistical.
For DDR5, DFE Equalization is needed. Discussions are ongoing about
whether/how IBIS-AMI can be used as a solution, given some limitations. I
think it's a bit premature to call out any methodology as standard yet.
At what datarate statistical analysis becomes really useful for DDR (maybe
because it takes too many UI to get all combinations in) is a separate
interesting topic. Maybe an interesting Designcon paper someday.
So as in my last sentence, I'm still a bit confused about what the question
is...
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [
mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Cheng, Chris
Sent: Friday, October 27, 2017 6:01 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Why do you think equalization can only be done by statistical analysis in DDR ?
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx / Email
4209 Technology Dr
Fremont, CA 94538
USA
-----Original Message-----
From: Bhagwath, Nitin [
mailto:Nitin_Bhagwath@xxxxxxxxxx]
Sent: Friday, October 27, 2017 5:30 PM
To: Cheng, Chris <chris.cheng@xxxxxxx>; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: EQ for DDR5
We need to separate the need for statistical analysis from the need for
equalization analysis. Both have been used for Serial links with IBIS-AMI, but
DDR5 really only needs support for DFE. If this involves requiring IBIS-AMI,
well, that's the fun conversation in the IBIS-AMI committee to make sure that
SSO, DQS, non-asymmetric and other limitations are worked around. An
industry-standard support is still a work-in-progress.
If you're talking only about being able to do SSO and incorporate DQS, well,
many tools support that today (including HyperLynx). Simply do a time-domain
simulation with a few thousand bits. The ringing should die down within a
couple of round-trips.
There's the answer. What's the question again?
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [
mailto:si-list-bounce@xxxxxxxxxxxxx] On ;
Behalf Of Cheng, Chris
Sent: Friday, October 27, 2017 5:00 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: EQ for DDR5
Single end source synchronous bus like DDR is very difficult to do statistical
analysis.
Single ended driver with active termination is most likely non-LTI. SSO is a
worst case analysis with odd and even mode SSO impact. Also, strobe placement
is different between read and write so SSO impact is different between the two
conditions. While protocol guarantee only 50% bus switching, nearby bit
switching will saturate the SSO impact within a few local bits. You always
simulate only the worst case impact because you're like to run into it in real
life.
DDR bus is very different from serial bus. The burst is mostly limit to 4x, 8x
bit for random cache line access. Deep BER analysis is really meaningless in
real life. Just pretty pictures.
However, protocol corner cases like strobe pre/postamble timing analysis is
important also. Leveling training is notoriously problematic.
Anyone who claim there is a package for DDR bus analysis better have answers to
the above.
Chris Cheng
Distinguished Technologist , Electrical
Hewlett-Packard Enterprise Company
+1 510 344 4439/ Tel
chris.cheng@xxxxxxx<
mailto:chris.cheng@xxxxxxx> / Email
4209 Technology Dr
Fremont, CA 94538
USA
[hpe-logo-sm]
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