[SI-LIST] Re: Distant Reference Planes Through Other Planes

  • From: "Brown, William G" <william.g.brown@xxxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 22 Jul 2003 15:59:55 -0400

Thanks for all the responses, sounds like this technique is used by several
people.  I do have one follow-up question however. 

Wouldn't there be a distance beyond which a reference plane would no longer
act as a reference plane for a controlled impedance line?  This was my
initial concern because for this board one of the planes would need to be 30
Mils away according to HyperLynx calculations and that's considerably more
than we've used in past designs.

The issue arises from a fairly high impedance (90 Ohms single-ended),
unwillingness to use lines smaller than 5 Mils and a tight overall board
thickness which prevents adding dedicated layers to accommodate the 90 Ohm
signals.

I am also concerned due to the large amounts of plane we'll have to
eliminate in order to ensure the reference planes 30 Mils away are the
closest planes to the impedance lines.  It's a backplane application as
well, so there is additional concern over plane integrity.

Any other comments? Thanks for the answers, I'm still learning on these type
issues.

Thanks,
Bill


> -----Original Message-----
> From: Ege Engin [SMTP:engin@xxxxxxxxxx]
> Sent: Friday, July 18, 2003 4:25 AM
> To:   si@xxxxxxxxxxxx
> Cc:   si-list@xxxxxxxxxxxxx
> Subject:      [SI-LIST] Re: Distant Reference Planes Through Other Planes
> 
> Kim,
> Neglecting the power/ground noise, the return currents for the stripline
> configuration can be determined with a simple equation. For such a case,
> the ratio of the return currents on the upper and lower planes is h1/h2,
> where h1, h2 are the thicknesses of the lower and upper substrates,
> respectively. The power/ground noise can also be included with a proper
> model, even for coupled striplines. We are planning to present the
> deatils of such a model soon, as well as some measurement results. 
> The paper "ectc_2002_pds.pdf" by Chun, again in the yahoo files library
> for this list, also has a discussion on this topic.
> 
> Ege  
> 
> Kim Flint schrieb:
> > 
> > Bill-
> > 
> > I've used this technique before to meet specific impedance requirements
> > that were otherwise incompatible with a particular layer geometry. In
> some
> > applications it is a reasonable approach and can work fine. (you didn't
> > mention what the goal was in your case.)
> > 
> > For example, say you have a layer mainly using 5mil traces at 50 ohms.
> Then
> > have a small number of 100 ohm diff pairs operating in the multi-ghz
> range
> > where you decide an 8 mil wide trace is needed to reduce skin effect
> loss.
> > You couldn't get 100 ohms using the same reference planes as the other
> > traces on that layer, but you might be able to do it by cutting out a
> > portion of those planes so that the diff pairs could reference the next
> > planes above/below.
> > 
> > You just need to redetermine the impedance of the special traces
> > considering the further-away reference planes, and carefully plan your
> > stackup and trace width so these traces continue to meet the required
> > impedance. (If it is a controlled impedance board, make sure to explain
> > what you are doing to the fab house or they will be calling you in the
> > middle of the night!) Crosstalk will be more significant since you are
> > further from the planes, so you will need to compensate with greater
> > spacing between traces. You will need to make sure the planes you are
> > cutting out are backed off appropriately all the way around so that they
> > don't impact impedance of the special traces. Obviously, you can't route
> > any other "normal" traces across the gap on any of the related signal
> > layers or they will suffer impedance discontinuities and big return
> current
> > loops.
> > 
> > As to your second question, whether it will be an issue to reference
> only
> > ground planes depends on the signaling technology involved. This has
> been
> > discussed a lot on this forum in the past, so it is probably best to go
> > back through the archives for a lot of detail on it. Most signaling
> > technology is ground referenced so using ground planes is usually a good
> > choice for critical signals in that respect. If I have to choose one or
> the
> > other, I would rather have a signal referenced between two ground planes
> > than two power planes for that reason. Especially if the power planes
> are
> > not the i/o power. Noise coupled into the signal from the power plane
> will
> > interfere with the receiver's ability to measure it w.r.t. ground.
> > 
> > But you do need to consider that when a cmos type driver draws current
> from
> > vcc to switch high, the current somehow needs to return to vcc at the
> > driver to complete the loop. If you only have ground planes adjacent to
> > your signal, then return current on those planes will have to pass
> through
> > capacitance on the die and/or your board decoupling caps to return to
> vcc.
> > At the 1-2ns rise times you say you have I would think that is fine,
> > assuming you've done a decent job of decoupling your power. However, I
> > think it is a bit better to have the trace sandwiched between an i/o
> power
> > and a ground plane, so on every switch half the current is returning
> from
> > one of the reference planes directly connected to the transistor. In
> order
> > to determine how much "a bit better" is, you would have to do some
> > simulation for your specific case.
> > 
> > Now that I'm thinking about it I'd like to study this a bit more myself.
> > Are there any papers available that analyze this situation in depth? I
> read
> > the paper by Larry Smith of Sun in the yahoo files library for this list
> > (epep_1999.pdf), which nicely illustrates SSN effects of only
> referencing
> > vcc or ground, but unfortunately doesn't go on to compare to the case of
> > using both. I'm rereading some of the other papers there that relate.
> Any
> > more references anybody can share?
> > 
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