Hi All, I have a scenario here where a designer wants to reference a plane through gaps in other planes. It makes me uncomfortable, so I'd like to know how to properly do this construction (or whether to avoid it completely) and what the issues are. For example, say a portion of the PCB stackup looks like this: GROUND PLANE SIGNAL 1 POWER PLANE (Gaps above signal routing on SIGNAL2) SIGNAL 2 (controlled impedance signals) POWER PLANE (Gaps below signal routing on SIGNAL 2) SIGNAL 3 GROUND PLANE Assuming that a relatively large gap is left in the planes, what are the other issues which need to be addressed and looked into? Some concerns I've thought might be applicable are what supplies are associated with the signals, should the signals reference a PWR & GND plane instead of two GND planes, are their return current issues and is there an issue with having your reference planes relatively distant (30 Mils) from the signal lines? Any comments on this practice would be appreciated. For argument's sake, assume we're running a couple hundred MHz with 1-2 ns rise times. Thanks, Bill ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu