[SI-LIST] Re: Distant Reference Planes Through Other Planes
- From: Kim Flint <si@xxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 17 Jul 2003 21:36:20 -0700
Bill-
I've used this technique before to meet specific impedance requirements
that were otherwise incompatible with a particular layer geometry. In some
applications it is a reasonable approach and can work fine. (you didn't
mention what the goal was in your case.)
For example, say you have a layer mainly using 5mil traces at 50 ohms. Then
have a small number of 100 ohm diff pairs operating in the multi-ghz range
where you decide an 8 mil wide trace is needed to reduce skin effect loss.
You couldn't get 100 ohms using the same reference planes as the other
traces on that layer, but you might be able to do it by cutting out a
portion of those planes so that the diff pairs could reference the next
planes above/below.
You just need to redetermine the impedance of the special traces
considering the further-away reference planes, and carefully plan your
stackup and trace width so these traces continue to meet the required
impedance. (If it is a controlled impedance board, make sure to explain
what you are doing to the fab house or they will be calling you in the
middle of the night!) Crosstalk will be more significant since you are
further from the planes, so you will need to compensate with greater
spacing between traces. You will need to make sure the planes you are
cutting out are backed off appropriately all the way around so that they
don't impact impedance of the special traces. Obviously, you can't route
any other "normal" traces across the gap on any of the related signal
layers or they will suffer impedance discontinuities and big return current
loops.
As to your second question, whether it will be an issue to reference only
ground planes depends on the signaling technology involved. This has been
discussed a lot on this forum in the past, so it is probably best to go
back through the archives for a lot of detail on it. Most signaling
technology is ground referenced so using ground planes is usually a good
choice for critical signals in that respect. If I have to choose one or the
other, I would rather have a signal referenced between two ground planes
than two power planes for that reason. Especially if the power planes are
not the i/o power. Noise coupled into the signal from the power plane will
interfere with the receiver's ability to measure it w.r.t. ground.
But you do need to consider that when a cmos type driver draws current from
vcc to switch high, the current somehow needs to return to vcc at the
driver to complete the loop. If you only have ground planes adjacent to
your signal, then return current on those planes will have to pass through
capacitance on the die and/or your board decoupling caps to return to vcc.
At the 1-2ns rise times you say you have I would think that is fine,
assuming you've done a decent job of decoupling your power. However, I
think it is a bit better to have the trace sandwiched between an i/o power
and a ground plane, so on every switch half the current is returning from
one of the reference planes directly connected to the transistor. In order
to determine how much "a bit better" is, you would have to do some
simulation for your specific case.
Now that I'm thinking about it I'd like to study this a bit more myself.
Are there any papers available that analyze this situation in depth? I read
the paper by Larry Smith of Sun in the yahoo files library for this list
(epep_1999.pdf), which nicely illustrates SSN effects of only referencing
vcc or ground, but unfortunately doesn't go on to compare to the case of
using both. I'm rereading some of the other papers there that relate. Any
more references anybody can share?
kim
At 02:24 PM 7/17/2003, Brown, William G wrote:
>Hi All,
>
>I have a scenario here where a designer wants to reference a plane through
>gaps in other planes. It makes me uncomfortable, so I'd like to know how to
>properly do this construction (or whether to avoid it completely) and what
>the issues are.
>
>For example, say a portion of the PCB stackup looks like this:
>
>GROUND PLANE
>SIGNAL 1
>POWER PLANE (Gaps above signal routing on SIGNAL2)
>SIGNAL 2 (controlled impedance signals)
>POWER PLANE (Gaps below signal routing on SIGNAL 2)
>SIGNAL 3
>GROUND PLANE
>
>Assuming that a relatively large gap is left in the planes, what are the
>other issues which need to be addressed and looked into?
>
>Some concerns I've thought might be applicable are what supplies are
>associated with the signals, should the signals reference a PWR & GND plane
>instead of two GND planes, are their return current issues and is there an
>issue with having your reference planes relatively distant (30 Mils) from
>the signal lines?
>
>Any comments on this practice would be appreciated. For argument's sake,
>assume we're running a couple hundred MHz with 1-2 ns rise times.
>
>Thanks,
>Bill
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