[SI-LIST] Re: Digital Interconnect
- From: Alexandre Desnoyers <alex@xxxxxxxx>
- To: Mohamad Haghtalab <mohaghtalab@xxxxxxxxx>
- Date: Mon, 24 Aug 2009 09:52:35 +0200
Hi Mohamad,
If you have access to Hyperlynx (or similar IBIS simulation software),
you can simulate the result without the termination resistor. I did a
similar investigation a few months ago and managed to avoid termination
resistor for QDR memory running at 250MHz. The result from the
simulation was that the waveform was within the datasheet parameters
regarding overshoot/undershoot _if_ (and only if) you keep the 50ohm
trace length below one inch. Then it was only a matter of placing and
routing the PCB to meet this requirement, which was not easy. By
avoiding ODT in the FPGA or parallel termination, we saved over 2 Watt,
or 1/10th of the total board power.
Regards,
Alex
Mohamad Haghtalab wrote:
> Hi all
>
> I'm working on a PCB which contains SRAMs connected to FPGA through
> striplines,i dont have enough space to implement source termination
> (inserting resistors) ,i think (is this true?)
> most of output resistor of digital I/O buffers are low e.g less than 30
> ohm,if we assume that this is true for the case we are using ,then is this
> good idea to route this lines in a
> lowest possible impedance?,with considering this fact that we have limitation
> in lowering the impedance of stripline what is the best work we should do to
> reach best design in terms of signal integrity issues without using of
> resistors for source termination?
>
> Thanks for Help
> Regards
> M.haghtalab
>
>
>
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