[SI-LIST] Re: Digital Interconnect

  • From: Jory McKinley <jory_mckinley@xxxxxxxxx>
  • To: Mohamad Haghtalab <mohaghtalab@xxxxxxxxx>, si-list@xxxxxxxxxxxxx
  • Date: Sun, 23 Aug 2009 12:10:17 -0700 (PDT)

Hello Mohamad,
Check if you have the option to turn on ODT at the load.  In this case you will 
not need source termination and should sweep various stripline impedance with 
various source driver and load ODT settings.  If you have no ODT then check if 
you have space to implement load termination (resistor to VDD/2) and then sweep 
your driver settings with various stripline impedances to determine timing and 
signal integrity.  Remember that you will need to simulate Address/Control in 
one direction and Data/Strobe in both directions.
Regards,
-Jory




________________________________
From: Mohamad Haghtalab <mohaghtalab@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Sunday, August 23, 2009 7:03:46 AM
Subject: [SI-LIST] Digital Interconnect

Hi all
 
I'm working on a PCB which contains SRAMs connected to FPGA through 
striplines,i dont have enough space to implement source termination (inserting 
resistors) ,i think (is this true?)
most of output resistor of digital  I/O buffers are low e.g less than 30 ohm,if 
we assume that this is true for the case we are using ,then is this good idea 
to route this lines in a
lowest possible impedance?,with considering this fact that we have limitation 
in lowering the impedance of stripline what is the best work we should do to 
reach best design in terms of signal integrity issues without using of 
resistors for source termination? 
 
Thanks for Help
Regards
M.haghtalab
 

      
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