[SI-LIST] Digital Interconnect
- From: Mohamad Haghtalab <mohaghtalab@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 23 Aug 2009 04:03:46 -0700 (PDT)
Hi all
I'm working on a PCB which contains SRAMs connected to FPGA
through striplines,i dont have enough space to implement source termination
(inserting resistors) ,i think (is this true?)
most of output resistor of digital I/O buffers are low e.g less than 30 ohm,if
we assume that this is true for the case we are using ,then is this good idea
to route this lines in a
lowest possible impedance?,with considering this fact that we have limitation
in lowering the impedance of stripline what is the best work we should do to
reach best design in terms of signal integrity issues without using of
resistors for source termination?
Thanks for Help
Regards
M.haghtalab
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