I hope, nobody was confused by my slip of pen -Â Cosmin Iorga is well known
specialist for many of SI-listers.
Thank you,Â
Iliya
On Wednesday, August 8, 2018, 11:18:27 PM PDT, Iliya Zamek
<dmarc-noreply@xxxxxxxxxxxxx> wrote:
I agree with good comments done by Cosmin, Istvan (Novak), and Scott.Â
From our experience, building pre-layout PDN model is very effective and will
give you possibility to simulate main PDN effects with relatively good
accuracy. Some companies are doing this, Cosmin Iotga, Larry Smith, and me also
have done some work and developed tools for PDN analysis.
 I have to note that there is no one universal PDN model for all cases. Which
model to choose depends on the source of a noise. When you consider Transient
processes due to die activities it needs to look from the die to the
package-board-capacitance, and good to include all parasitic. When looking for
the external to die noise it needs to look from the noise source to the die.
For the external noise case you may simulate noise propagation from noise
source to the BGA ball; the pass from BGA ball to the die does not contribute
much, especially for low frequency noise.
The capacitor mounting inductance considered in some publications; you might
found some information in Larry paper where he described his calculator - look
in our mutual Tutorial in DesignCon 2015. Â
Thank you.
Iliya Zamek Â
  On Wednesday, August 8, 2018, 12:52:15 PM PDT, Istvan Nagy
<buenoshun@xxxxxxxxx> wrote:Â
Hi,
Thanks.
I know the basic problem is the PDN is more wrapped around the
discontinuities than a long serdes channel. I'm trying to find a solution
to that problem.
The problem with simulating the whole PDN together is that this method is
only good as post layout final verification, tedious setup, overnight sim
run. I need a front-end DESIGN (not verification) method that is fast, that
allows varying one parameter and quickly checking the effect of the change
on the whole system. That can only be provided by decomposition and
"schematic-level" simulation of the PDN. The only missing link for that is
the capacitor mounting inductance.
People often refer to the mounting inductance of a capacitor: so it must
exist, this concept must be based on real physical measurable stuff.
Another issue is why I am not sure that the closest plane is the right
place for the simulation port is that the purpose of the PDN is to provide
flat/low impedance PDN to the ASIC chip, not to the capacitor or to itself.
This question is still open...
Regards,
Istvan Nagy
On Wed, Aug 8, 2018 at 6:36 AM, Istvan Novak <istvan.novak@xxxxxxxxxxx>
wrote:
Hi Istvan,
This is a tricky question. As you know the basic SI rule, it is never a
good idea to cut a structure for measurement or for simulations in the
middle of discontinuities. When we attempt to model only the mounting
structure of a component by leaving the component itself out of the
picture, the result will have no information about the coupling between
your board or package model and the component you left out, leaving an
uncertainty of the result when you try to merge the pieces. As Scott
pointed out, for high-frequencies, you just need the 'lower contour' of the
current path in the capacitor to include in your composite geometry.
If you need to accuracy at higher frequencies, it is always a good idea to
have something simple about your component in the model and cut the
structure further away.
Regards,
Istvan Novak
On 8/8/2018 3:03 AM, Istvan Nagy wrote:
Hi,
We are trying to determine the inductance of decoupling capacitor
mounting structures.
Should we simulate capacitor+via seen from the ASICââ¬â¢s BGA ball, or
capacitor+via seen from the power plane?
I would substitute a 0R short for the cap, and place the simulation
ports on the plane layer underneath or on the BGA land pad. If we simulate
caps from the plane, then we also simulate the BGA pads from the plane and
add this inductance to the excitation current source (that represents the
ASIC chip) in the ADS. It may be good either way for small caps directly
under the BGA on the bottom side, although Iââ¬â¢m not sure. But what
about
somewhat larger capacitors on top/bottom outside the BGA area, far from
ASIC power pins? Then we may get ââ¬Åfakeââ¬Â inductance due to the
large
distance from the BGA pads? I read somewhere that the capacitors have to
have low inductance to the plane only, not relative to the ASIC power pin
BGA balls, and ASIC to plane inductance is a separate thing. How is this
really?
If we simulate from the plane, which plane? There might be 4 power
planes and 8 gnd planes for the same rail.
Will any of this include the plane spreading inductance?
In an HFSS setup, I was thinking on having just a strip of copper on the
plane layer for the simulation, to get the loop inductance without the
plane capacitance and resonance that will be modeled separately. The point
is to simulate different parts of the PDN separately, without overlapping
effects between the sub-models. We would simulate each cap mounting type,
the plane, the VRM (measured on eval board, not sim), the BGA-viaââ¬Â¦all
separately in 3D, and then later plug the models together in an ADS
schematics. Then we can vary one parameter and quickly re-run, for design
optimization. For high-speed serdes signal channels people do
decompositional analysis and plug the sub-models together, pretty common. I
want to do the same for the PDN, but itââ¬â¢s a bit harder to separate
the
elements without overlapping effects.
Best regards,
Istvan Nagy
Hardware engineer
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