From my experience questions like this can always be explained by the
fundamental concepts of transient electric currents flowing through the PDN.
For example, the mounting inductance influences the self-generated transient
currents of the circuits on die so from this perspective we need to look from
the die. The decoupling capacitors also reduce external generated noise that
would otherwise propagate into the die, so from this perspective we need to
look from the PCB. I suggest you build a simple model of the die+package+PCB
and try to "manually" calculate the mounting inductance by first understanding
the path of transient current flow and from this analysis decide which
PCB/package/die structures participate and which don't participate to the
transient current path. This is what I emphasize in my power integrity and
noise coupling course that I teach at UCLA Extension. You can take a look at
an example course project and the calculations done in there - here is a link
to download it (the sample course project link is at the bottom of the page -
loads slowly so please be patient)
http://www.piscanner.com/patents-and-publications
Best Wishes,
Cosmin
--------------------------------------------
On Wed, 8/8/18, Istvan Nagy <buenoshun@xxxxxxxxx> wrote:
Subject: [SI-LIST] Re: Decoupling capacitor inductance simulation, PDN
decomposition
To: "Istvan Novak" <istvan.novak@xxxxxxxxxxx>
Cc: "SI" <si-list@xxxxxxxxxxxxx>
Date: Wednesday, August 8, 2018, 11:51 AM
Hi,
Thanks.
I know the basic problem is the PDN is more
wrapped around the
discontinuities than a
long serdes channel. I'm trying to find a solution
to that problem.
The problem
with simulating the whole PDN together is that this method
is
only good as post layout final
verification, tedious setup, overnight sim
run. I need a front-end DESIGN (not
verification) method that is fast, that
allows varying one parameter and quickly
checking the effect of the change
on the
whole system. That can only be provided by decomposition
and
"schematic-level" simulation
of the PDN. The only missing link for that is
the capacitor mounting inductance.
People often refer to the mounting inductance
of a capacitor: so it must
exist, this
concept must be based on real physical measurable stuff.
Another issue is why I am not sure that the
closest plane is the right
place for the
simulation port is that the purpose of the PDN is to
provide
flat/low impedance PDN to the ASIC
chip, not to the capacitor or to itself.
This question is still open...
Regards,
Istvan Nagy
On Wed, Aug 8, 2018 at 6:36 AM, Istvan Novak
<istvan.novak@xxxxxxxxxxx>
wrote:
HiIstvan,
tricky question. As you know the basic SI rule, it is
This is a
good idea to cut a structurefor measurement or for simulations in the
middle of discontinuities. When weattempt to model only the mounting
structure of a component by leaving the component itself out
picture, the result will have noinformation about the coupling between
your board or package model and the component you left out,
uncertainty of the resultwhen you try to merge the pieces. As Scott
pointed out, for high-frequencies, youjust need the 'lower contour' of the
current path in the capacitor to includein your composite geometry.
frequencies, it is always a good idea to
If you need to accuracy at higher
have something simple about your componentin the model and cut the
structurefurther away.
Regards,
Istvan NovakOn 8/8/2018 3:03 AM, Istvan Nagy wrote:
are trying to determine the inductance of decoupling
Hi,
We
structures.mounting
seen from the ASIC’s BGA ball, or
Should we simulate capacitor+via
plane?capacitor+via seen from the power
the cap, and place the simulation
I would substitute a 0R short for
underneath or on the BGA land pad. If we simulateports on the plane layer
simulate the BGA pads from the plane andcaps from the plane, then we also
excitation current source (that represents theadd this inductance to the
good either way for small caps directlyASIC chip) in the ADS. It may be
although I’m not sure. But what aboutunder the BGA on the bottom side,
top/bottom outside the BGA area, far fromsomewhat larger capacitors on
“fake†inductance due to the largeASIC power pins? Then we may get
somewhere that the capacitors have todistance from the BGA pads? I read
only, not relative to the ASIC power pinhave low inductance to the plane
inductance is a separate thing. How is thisBGA balls, and ASIC to plane
simulate from the plane, which plane? There might be 4really?
If we
for the same rail.planes and 8 gnd planes
spreading inductance?
Will any of this include the plane
on having just a strip of copper on the
In an HFSS setup, I was thinking
get the loop inductance without theplane layer for the simulation, to
that will be modeled separately. The pointplane capacitance and resonance
the PDN separately, without overlappingis to simulate different parts of
would simulate each cap mounting type,effects between the sub-models. We
eval board, not sim), the BGA-via…allthe plane, the VRM (measured on
plug the models together in an ADSseparately in 3D, and then later
parameter and quickly re-run, for designschematics. Then we can vary one
serdes signal channels people dooptimization. For high-speed
the sub-models together, pretty common. Idecompositional analysis and plug
but it’s a bit harder to separate thewant to do the same for the PDN,
effects.elements without overlapping
Istvan Nagy
Best regards,
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