Hi Istvan,
This is a tricky question. As you know the basic SI rule, it is never a
good idea to cut a structure for measurement or for simulations in the
middle of discontinuities. When we attempt to model only the mounting
structure of a component by leaving the component itself out of the
picture, the result will have no information about the coupling between
your board or package model and the component you left out, leaving an
uncertainty of the result when you try to merge the pieces. As Scott
pointed out, for high-frequencies, you just need the 'lower contour' of
the current path in the capacitor to include in your composite geometry.
If you need to accuracy at higher frequencies, it is always a good idea
to have something simple about your component in the model and cut the
structure further away.
Regards,
Istvan Novak
On 8/8/2018 3:03 AM, Istvan Nagy wrote:
Hi,
We are trying to determine the inductance of decoupling capacitor
mounting structures.
Should we simulate capacitor+via seen from the ASIC’s BGA ball, or
capacitor+via seen from the power plane?
I would substitute a 0R short for the cap, and place the simulation
ports on the plane layer underneath or on the BGA land pad. If we
simulate caps from the plane, then we also simulate the BGA pads from
the plane and add this inductance to the excitation current source
(that represents the ASIC chip) in the ADS. It may be good either way
for small caps directly under the BGA on the bottom side, although
I’m not sure. But what about somewhat larger capacitors on
top/bottom outside the BGA area, far from ASIC power pins? Then we
may get “fake†inductance due to the large distance from the BGA
pads? I read somewhere that the capacitors have to have low
inductance to the plane only, not relative to the ASIC power pin BGA
balls, and ASIC to plane inductance is a separate thing. How is this
really?
If we simulate from the plane, which plane? There might be 4 power
planes and 8 gnd planes for the same rail.
Will any of this include the plane spreading inductance?
In an HFSS setup, I was thinking on having just a strip of copper on
the plane layer for the simulation, to get the loop inductance
without the plane capacitance and resonance that will be modeled
separately. The point is to simulate different parts of the PDN
separately, without overlapping effects between the sub-models. We
would simulate each cap mounting type, the plane, the VRM (measured
on eval board, not sim), the BGA-via…all separately in 3D, and then
later plug the models together in an ADS schematics. Then we can vary
one parameter and quickly re-run, for design optimization. For
high-speed serdes signal channels people do decompositional analysis
and plug the sub-models together, pretty common. I want to do the
same for the PDN, but it’s a bit harder to separate the elements
without overlapping effects.
Best regards,
Istvan Nagy
Hardware engineer
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