[SI-LIST] Re: DecapPlacement
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: sreekanthn@xxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 12 Mar 2007 21:53:21 -0700 (PDT)
Hello Sreekanth,
Rules of thumb are dangerous here and should be used as a starting point only
(such as layered cap size from VRM to IC's) since resonances can be tricky. I
would strongly consider using a tool like Siwave, Sigrity, Optimal or your
choice to find your boards resonances and therefore decoupling cap placement.
Remember board decoupling strategies are only effective up to a point and a
very good understanding of the package(s) and on-die parasitics is critical.
-Jory
Sreekanth N nampoothiri <sreekanthn@xxxxxxxxxxxxxxx> wrote: Dear Group,
How much ll be the bad effect if we place a decap in the
opposite side of the mother IC,if the design is in 200+ MHz range?
Do we have any rule of thumb regarding the decap
handling?
Best Regards,
Sreekanth N Nampoothiri
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Jory McKinley
McKinley Consulting
e-mail: jory_mckinley@xxxxxxxxx
phone: (508)624-7103
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