[SI-LIST] Re: DecapPlacement

  • From: "Javier DeLaCruz" <jdelacruz@xxxxxxxxxxxx>
  • To: <sreekanthn@xxxxxxxxxxxxxxx>
  • Date: Fri, 16 Mar 2007 01:54:30 -0400

The best side to place decoupling capacitors tends to vary by package
and PCB design.  Some of these points have already been stated by our
peers but I'd like to put this in more tangible terms by giving you
examples.=20

The bottom line is that you generally want to provide the highest
capacitance (or at least sufficient capacitance) with the least amount
of series inductance.  The capacitors themselves have series inductance
as well so don't forget to consider this, but let's assume we are only
using one capacitor. =20

In a conventional mostly digital layout, there will be many signals to
route from the smallest package that can support these.  This is usually
laid out such that many signals are on the edge so that you can route
many of them without vias in the PCB.  This will typically force you to
place any component side capacitors further away from a package since
the area near the package will be dominated by routing.  In this case,
the capacitors are more effectively placed on the bottom side (opposite
of the package) so that the series inductance to the package is
minimized.  Having many vias and capacitors will help in reducing the
series inductance since you can divide it over more electrical paths.
Therefore, in this case, it is best to have capacitors on the PCB
backside below the package in the field of vias.

A contrary case would be a typical high speed mostly analog board such
as an optical network card with 5G, 10G or 40G signals.  These types of
devices will tend to have fewer signals and lots of shielding on the
component side of the PCB.  Here, your lowest inductance path for the
capacitors may likely be on the top side since the wide shielding on the
top layers will have less inductance than the path through the backside.
Since VSS will normally be the shielding on the top layer, followed by
VDD on the second or third layer (if VSS is used again on the second
layer), the inductive path through the capacitors will just be comprised
of very wide metal planes and a very short via (metal-1 to metal-2 or 3)
twice.  Not having to fit between the vias in the array below the
package will also allow you to use larger less expensive capacitors.
Therefore, in this case, having the caps on the top side would be
better.

You'll also need to consider caps to stabilize a PCB resonance or
provide for local energy storage to prevent supply collapse if the power
source is far from the component.  For these, it doesn't really matter
which side these types of caps are on. =20

Regards,
Javier DeLaCruz
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Lee Ritchey
Sent: Thursday, March 15, 2007 1:38 PM
To: Jack Olson; sreekanthn@xxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DecapPlacement

If your planes are continuous, there is little benefit to placing
capacitors on one side of a PCB vs. the other.  All that might be
achieved
in a slightly lower mounting inductane based on how deep into the PCB
the
vias have to reach to connect to the planes.  However, this delta L only
moves the self resonant frequency of the capacitors a little higher or
lower.  In a normal PCB, this is not enough of a gain to warrant
penalizing
assembly by placing capacitors on the bottom the PCB, if so doing
results
if double sided assembly.=20

There are many papers published that support this.

Lee Ritchey

Speeding Edge


> [Original Message]
> From: Jack Olson <pcbjack@xxxxxxxxx>
> To: <sreekanthn@xxxxxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 3/14/2007 8:07:08 PM
> Subject: [SI-LIST] Re: DecapPlacement
>
> We put nearly ALL of our decoupling on the back.
> Remember that even if the components are side by side,
> the vias still have to get to the planes and back, making it
> often the same electrical distance away. In other situations
> the distance is even closer from the back because the
> decoupling part can be placed directly under the power
> pad, rather than being placed some distance away for
> package size clearances.
> best wishes,
> Jack
>
>
> On 3/12/07, Sreekanth N nampoothiri <sreekanthn@xxxxxxxxxxxxxxx>
wrote:
> >
> > Dear Group,
> >
> >                    How much ll be the bad effect if we place a decap
in
> > the
> > opposite side of the mother IC,if the design is  in 200+ MHz range?
> >                    Do we have any rule of thumb regarding the decap
> > handling?
> >
> >
> > Best Regards,
> > Sreekanth N Nampoothiri
> >
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