[SI-LIST] Re: DecapPlacement
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Thu, 15 Mar 2007 21:58:37 -0400
Steve's point is that good engineering needs to be done to determine
whether or not a particular bypass capacitor solution is viable or not.
Every solution has trade offs. However, there are hard limits to the
physics of power delivery that are ignored only at the peril of the
designer. Those hard limits start with an understanding of the
device(s) being bypassed.
Sometimes back side bypass works. Sometimes it does not. Adding vias
to decrease mounted inductance may help, or it may not, depending on the
location of the planes, and the desired target impedance. Our approach
is a holistic one, starting at the power requirements and design of the
device package, and working down to the PCB plane stack-up and bypass
solution.
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
William Kitchen wrote:
> Aside from SI considerations, decaps on the back are almost
> always better for just getting everything to fit in a dense
> layout, and for leaving more room for vias, making routing
> easier. This could have some indirect SI benefit just by
> making routing a little neater. And for BGA's, back side is
> the only way to get the caps close to the power/gnd IC
> pads. So for these reasons, I put most decoupling caps on
> the back.
>
> Whenever I can, I double up on the vias to reduce the
> inductance. For example, if I have a cap on the back side
> of the pads on a flatpack, I'll put vias at both ends of
> each power or gnd IC pad, and connect the associated cap
> pad to both of these on the opposing side. This sometimes
> is impossible or impractical due to very fine pitch parts,
> or very dense layouts where I just can't afford many extra
> vias. But I do it where I can, especially for components
> that I know will have very fast rise/fall, fast clocks, or
> lots of signals switching simultaneously.
>
> Boards that have filled and plated vias for via-in-pad work
> out especially nice for back side caps. The via can go
> straight from the IC pad on one side to the cap pad on the
> other, hitting the plane on the way. No traces at all.
> 0402 caps can sit directly on top of adjacent power/gnd
> vias on 1mm or .8mm BGA's this way. This not only shortens
> the connections to the decaps, but it also allows more of
> them to fit in the area under the BGA since their placement
> is not limited to the channels left by a dog bone fanout.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jack Olson
> Sent: Thursday, March 15, 2007 10:27 AM
> To: steve weir
> Cc: sreekanthn@xxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: DecapPlacement
>
>
> Yes, I agree with you.
> The point of my reply was that it seemed like he
> was assuming that putting components on the
> back would automatically degrade the performance,
> ("how much be the bad effect")
> which is not a good assumption.
>
> thanks,
> Jack
>
>
> On 3/15/07, steve weir <weirsi@xxxxxxxxxx> wrote:
>
>> Jack, the plane and back for same side mounting versus bottom to top
>> is a bit more complicated. Which works better depends on:
>>
>> Location and quantity of Vcc / Vss balls on the package.
>> Location and quantity of Vcc / Vss via pairs into / through the PCB
>> Location of Vcc / Vss cavities in the stack-up, including of course
>> their separation.
>>
>> When engineered properly, backside caps can do the job just fine. In
>> a 4 / 6 layer design, backside caps can be superior to top side
>> caps. However the engineering to insure that either configuration is
>> adequate has to begin with the IC package design. The package must
>> consider the intended PCB environment or the designer is asking for
>> trouble.
>>
>> Regards,
>>
>>
>> Steve.
>> At 07:37 PM 3/14/2007, Jack Olson wrote:
>>
>>> We put nearly ALL of our decoupling on the back.
>>> Remember that even if the components are side by side,
>>> the vias still have to get to the planes and back, making it
>>> often the same electrical distance away. In other situations
>>> the distance is even closer from the back because the
>>> decoupling part can be placed directly under the power
>>> pad, rather than being placed some distance away for
>>> package size clearances.
>>> best wishes,
>>> Jack
>>>
>>>
>>> On 3/12/07, Sreekanth N nampoothiri <sreekanthn@xxxxxxxxxxxxxxx> =
>>>
> wrote:
>
>>>> Dear Group,
>>>>
>>>> How much ll be the bad effect if we place a =
>>>>
> decap
>
>> in
>>
>>>> the
>>>> opposite side of the mother IC,if the design is in 200+ MHz =
>>>>
> range?
>
>>>> Do we have any rule of thumb regarding the =
>>>>
> decap
>
>>>> handling?
>>>>
>>>>
>>>> Best Regards,
>>>> Sreekanth N Nampoothiri
>>>>
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