Hello Peri,
the load board that I mentioned is something that DRAM vendors use to
characterize their DRAMs.
it is not just the load board that you would need, for some test you
would need some DRAM vendor internal functionality.
E.g to measure Vout high you should drive a single rising edge and have
then a DC high level that you can measure.
Most likely you can not just build a load board where you measure this
parameter (same for the slew rates that you mentioned).
you would need to write defined data into the DRAM, disconnect the DQ
line, connect the ideal reference load, drive a the single edge, stop
the clock, measure Vouthigh.
Much simpler is if you have access to internal DRAM functions that just
drive out a high while connected to the reference load.
But how to access such a function will not be shared by the DRAM vendor.
This is anyhow just required if you want to verify the DRAMs device
verification. This is nothing that helps to measure anything that is
related to your system!
Yes, it is required to configure DRAM drive strength and Controller
Drivestrength for Read based on your system.
But this can not be done with the standard functions of the Scopes DRAM
compliance application (at least not for the ones I know .. and I guess
I know all of them ;-)
(.. but just some time ago somebody told me from a new one .. I did not
check what this one is really measuring .. not sure if their Engineers
are listening ?!?! ... maybe I should check them... )
This is still manual engineering work .. and as mentioned in the other
e-mail that I sent ..
This is not the easy stuff .. this is one of the most difficult
measurements that I know.
You might not be able to use the application to measure any parameters
for the READS, but you can use the applications function to display a
source syncrounus dataeye for reads when measuring at the controller and
de-embedding the controller package (this is usually to big to be
ignored at this speed). This might be enough for you to optimize the
settings.
Best regards
Hermann
Our next Events:
visit us on "embedded world 2017"
14.03-16.03.2017 - Hall A2, Booth 651
EKH - EyeKnowHow
Signal Quality - Made in Bavaria
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
Am 25.01.2017 um 19:34 schrieb Periyasamy Iyyamperumal:
HI Hermann,
Thanks for the response.
I would like to know more about Load board that you are referring to.
Basically in the wave form, we are seeing non monotonous issue and the tool
is measuring the slew rate from the second non monotonous curve.
FPGA is the memory controller interfaced with DDR3L .
Is this problem occurs due to measurement setup or anything that we need to
do with Board layout? Or
Any changes to be done at Controller drive strength or different
termination can solve this problem
Regards
Peri
On Wed, Jan 25, 2017 at 1:02 PM, Hermann Ruckerbauer <
Hermann.Ruckerbauer@xxxxxxxxxxxxx> wrote:
Hello,
SRQseR & SRQseF are output parameters of the DRAM. these need to be
measured on a special load board (Reference load: ideal 25 Ohm termination
into VTT)) and con not be measured in the system.
They need to be tested guaranteed by the DRAM vendor.
With most DRAM compliance application you can not verify System reads, but
only the Data output of the DRAM (and this is the DRAM vendors job)
best regards
Hermann
Our next Events:
visit us on "embedded world 2017"
14.03-16.03.2017 - Hall A2, Booth 651
EKH - EyeKnowHow
Signal Quality - Made in Bavaria
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
Am 25.01.2017 um 17:50 schrieb Periyasamy Iyyamperumal:
Dear All,the
I request your suggestions on the below test validation failure of Slew
rate on DDR3L Data bus during read mode.
DDR3L is fails on SRQseR & SRQseF. Also waveforms are non-monotonous in
nature, may be due to this, we may see the failure result.------------------------------------------------------------------
Could you please provide your suggestions/feed back, how we can over come
on this?
Is there any settings on Memory Controller to control the slew rate/to
achieve good waveform?
Is there any relationship between Slew rate and Setup/hold time?
Do we need to validate Write burst Slewrate?
Test Setup:
Using *Key sight DDR3 validation software*
Slew rate failure while DDR3L read burst validation
Below are the test report generated by keysight ddr3 validation software.
*Pass Limits as per JEDEC: 1.75 V/ns to 5.0 V/ns*
*Actual Values: SRQseR 420.28 mV/ns*
Number of Burst Measured: 1
Number of Meas: 54.0
SRQseR_time:642ps
Vref: 675mV
Voh_ac: 540mV
PUT: DQ0
Supporting Pin: DQS0/DQS0#
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
