Dear All,
I request your suggestions on the below test validation failure of Slew
rate on DDR3L Data bus during read mode.
DDR3L is fails on SRQseR & SRQseF. Also waveforms are non-monotonous in the
nature, may be due to this, we may see the failure result.
Could you please provide your suggestions/feed back, how we can over come
on this?
Is there any settings on Memory Controller to control the slew rate/to
achieve good waveform?
Is there any relationship between Slew rate and Setup/hold time?
Do we need to validate Write burst Slewrate?
Test Setup:
Using *Key sight DDR3 validation software*
Slew rate failure while DDR3L read burst validation
Below are the test report generated by keysight ddr3 validation software.
*Pass Limits as per JEDEC: 1.75 V/ns to 5.0 V/ns*
*Actual Values: SRQseR 420.28 mV/ns*
Number of Burst Measured: 1
Number of Meas: 54.0
SRQseR_time:642ps
Vref: 675mV
Voh_ac: 540mV
PUT: DQ0
Supporting Pin: DQS0/DQS0#
--
Please let me know if you have any further clarifications.
Thanks and Regards
Peri
Mobile:+1 631 542 3845
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
