Hello,
it's not jsut only the test point.
The compliance app tests the data output timings, not the Read timings.
The data output needs to be measured with a defined testload at the ball
of the DRAM.
this is not available in the system.
And: you can not configure this parameter. It just does not make sense
to measure this in the system. it does not say anything about your
system .. this and all other read parameters are DRAM characterization
parameters.
If you want to verify system reads you can do the following:
Configure your compliance software to use DQS to DQ skew as Read/write
separation
Delay your DQS by half a UI.
take your Controller datasheet and define the limits of your test
Take a testpoint close to the Controller
De-embedd the huge Controller package from teh measurement
Run Write tests to get setup/hold results
think about if your controller hast the ability to configure the
internal DQS delay in a way that it can capture the data correctly
Have fun!
Hermann
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Am 25.01.2017 um 20:03 schrieb Joseph.Schachner@xxxxxxxxxxxxxxxxxx:
Oh my yes, I have to agree with Ravinder Ajmani.
There are two reasonable places to make a measurment: 1) at the source 2)
at the termination (might not be matching impedance). In between the
signal you see on the line can look HORRIBLE, particularly if the memory
is not supplying a matching termination - which is common in DDR stuff to
save power.
And that may not be the only source of reflection. Any reflections will
make mid-bus measurements look horrible. It is hard to overstate how
messed up they can look. Just get your probe on (or within a small
fraction of an inch of) the FPGA pin/ball/whatever, and your problem will
probably be solved.
--- Joe S.
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