[SI-LIST] Re: DDR3 CK/CK# termination

  • From: "Moran, Brian P" <brian.p.moran@xxxxxxxxx>
  • To: "Sinha, Snehamay" <snehamay@xxxxxx>, Si-List <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 4 Jan 2012 03:04:39 +0000

Snehamay,

The decision to use the AC coupled or floating termination on CLK was made 
slightly before my time, and don't take this as gospel, but I seem to recall it 
was an attempt to tighten the CLK VIX range by allowing the virtual Vtt voltage 
to float, and thereby provide somewhat of a feedback loop in countering the 
impact of duty cycle variation and rise fall mismatch on VIX level, but don't 
quote me on that. I remember at the time the module TG was concerned about VIX 
and this termination scheme was judged to have some advantage in terms of VIX 
tolerance. That is my recollection, for what its worth. If you are working on a 
memory down design I don't think there is a problem using a traditional Vtt 
termination on CLK. 

Brian Moran
Signaling Development Group
Client Platforms
Intel Corporation

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Sinha, Snehamay
Sent: Tuesday, January 03, 2012 2:34 PM
To: Si-List
Subject: [SI-LIST] DDR3 CK/CK# termination


Hi,
 I was looking at the JEDEC spec for DDR3 DIMMs and saw that the termination 
for the CK/CK# is through a capacitor to VDDQ. Why is this? Wouldn't it be 
simpler to connect the midpoint of the termination resistors to VTT without the 
capacitor.

regards,
Snehamay


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