[SI-LIST] DDR3 CK/CK# termination
- From: "Sinha, Snehamay" <snehamay@xxxxxx>
- To: Si-List <si-list@xxxxxxxxxxxxx>
- Date: Tue, 3 Jan 2012 22:33:31 +0000
Hi,
I was looking at the JEDEC spec for DDR3 DIMMs and saw that the termination
for the CK/CK# is through a capacitor to VDDQ. Why is this? Wouldn't it be
simpler to connect the midpoint of the termination resistors to VTT without the
capacitor.
regards,
Snehamay
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