[SI-LIST] Re: DDR3 1600 slew rate
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: jessica_wuluan@xxxxxxxxx
- Date: Tue, 08 May 2012 07:45:33 +0200
Hello Jessica,
the DRAM specification is designed to allow Point to Multipoint
connections. Especially the Derating is implemented to take care of
systems with very high load. The part for slew rates higher than 1V/ns
is in the table, but was not really discussed in much detail. Targtet
was to take care of systems with many DRAMs in parallel which will have
a low slew rate.
It is not the PCB slew rate degradation, but the input load of the DRAMs
that will reduce the slew rate ...
Hermann
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schrieb jing wu:
> Hi, All :
>
> I am confused when reading the derating table of DDR3 1600. In Jedec, the
> derating value is zero for slew rate 1v/ns. But for DDR3 1600, the data
> period is 625ps and swing level is 1.5V, so the DDR3-1600 SDRAM/Controller
> output buffer slew rate will be at least 1.5v/312.5ps=4.8v/ns. By adding the
> PCB degradation and SSN noise, the slew rate at the receiver still should be
> be much larger than 1v/ns. I did some simulation and turns out that the slew
> rate of DQ at receiver is about 4v/ns. Is it a typical slew rate value of
> DDR3 1600?
>
>
> Thanks,
> Jessica
>
>
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