[SI-LIST] Re: DDR2 termination Questions
- From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
- To: Hithesh <hitheshn@xxxxxxxxx>
- Date: Sat, 28 Apr 2012 18:58:26 +0200
Hello Hitesh,
DRAM interface ciruits are usually not exactly matched. This is a
tradeoff voltage vs. Timing. You could either select predefined values,
or optimize the circuit on your own by simulation.
As mentioned, on DRAMs you do have often a point to multipoint bus, and
the system is optimized for such a usage. Even not perfect for a point
to point connection this should work as well as this configuration will
give you more margin.
If you don't trust the predefined values from design guides or your FPGA
vendors you need to simulate your system.
Hermann
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schrieb Hithesh:
> Here's the circuit (I used LTspice) -
> http://images.elektroda.net/67_1335628756.png
>
> @Hermann
> Let's just assume the DDR output impedance is ~30 ohms, so you need
> another 20 ohms in series to match it with the Tx line.
> Let's also assume there's no DCI or ODT on the FPGA, just for the sake
> of argument.
>
>
> Regards,
> -Hithesh
>
>
>
> On Sat, Apr 28, 2012 at 7:12 PM, Hermann Ruckerbauer
> <hermann.ruckerbauer@xxxxxxxxxxxxx
> <mailto:hermann.ruckerbauer@xxxxxxxxxxxxx>> wrote:
>
> Hello Hithesh,
>
> If your FPGA provides an OnDie Termination (what I would expect and
> somehowr read from your e-mail) usually there is no need for
> additional
> Series termination on the PCB. Is there any specific reason why
> you want
> to add this resistor ?
>
> The termination to midlevel (VTT) is part of the spec. Reasons why
> DRAM
> interconnects are not terminated to GND are the process technology of
> DRAMs (this would even prefer a high level termination) and the
> Point to
> multipoint communiction on DRAM busses (if your drivestrength is
> always
> the same, but different numbers of DRAMs are terminating this will
> shift your eye center level. if all DRAMs terminate to midlevel
> the Eye
> center voltage will be the same (just the swing will change).
>
> your voltage swing will be symmetrical arround VTT. And the hight will
> depend on drivestrength and termination settings. As Steve
> mentioned the
> swing can be calculated when you draw the circuit.
>
> Hermann
>
>
>
> Our next Events:
> ================
>
> "Open the Black Box of Signal Integrity"
> Seminar on 07. May 2012
> "Open the Black Box of Memory"
> Seminar on 09/10. October 2012
>
> Check our website or contact us for details
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de <http://www.EyeKnowHow.de>
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Veilchenstrasse 1
> 94554 Moos
> Tel.: +49 (0)9938 / 902 083
> Mobile: +49 (0)176 / 787 787 77
> Fax: +49 (0)3212 / 121 9008
>
>
> schrieb Hithesh:
> > Some questions about DDR2 termination -
> > Let's say it's a Read operation from Memory to FPGA
> >
> > DDR2 ---> series termination res--->50 ohm PCB Tx line -->50 ohm
> > termination resistor at FPGA to Vtt.
> >
> > Why should the 50 ohm resistor be terminated to Vtt, why not
> ground (like
> > RF amplifiers)?
> >
> > Is the DDR2 output voltage 1.8v? If yes, then the max voltage at
> FPGA will
> > be 0.9v.
> >
> > Thanks,
> > -Hithesh
> >
> >
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