[SI-LIST] DDR2 termination Questions
- From: Hithesh <hitheshn@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sat, 28 Apr 2012 17:37:49 +0530
Some questions about DDR2 termination -
Let's say it's a Read operation from Memory to FPGA
DDR2 ---> series termination res--->50 ohm PCB Tx line -->50 ohm
termination resistor at FPGA to Vtt.
Why should the 50 ohm resistor be terminated to Vtt, why not ground (like
RF amplifiers)?
Is the DDR2 output voltage 1.8v? If yes, then the max voltage at FPGA will
be 0.9v.
Thanks,
-Hithesh
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