[SI-LIST] Re: DDR2 termination Questions

  • From: Hithesh <hitheshn@xxxxxxxxx>
  • To: Ihsan Erdin <erdinih@xxxxxxxxx>
  • Date: Mon, 30 Apr 2012 00:50:02 +0530

Ishan,
If you use external parallel termination on both Fpga and ddr2, wouldn't
the signal swing (around Vref) be reduced?

-Hithesh



On Sun, Apr 29, 2012 at 6:33 PM, Ihsan Erdin <erdinih@xxxxxxxxx> wrote:

> Hithesh,
>
> If I remember correctly (you can verify it from JEDEC) the configuration
> you showed is intended for unidirectional DDR address/control/command lines
> which are driven by the controller only. In that case, the circuit must be
> reversed, such that the pullup termination to Vtt must be close to the DRAM
> input not the FPGA. When DRAM drives the clock or data busses on the read
> mode JEDEC doesn't specify (and you wouldn't need) a pullup termination at
> the controller (FPGA) input.
>
> Even on the address/control bus the pullup termination is kind of
> optional. My experience has been that it helps reflections at the expense
> of a reduced voltage swing. As such, it is a matter of a design issue. If
> the voltage at the DRAM input meets the logic threshold levels with Vtt
> termination it is arguably a good practice to design for low reflections.
> Otherwise you may have to remove the termination.
>
> As for your original question, the reference voltage for DDR is not 0V but
> the mid-point hence the connection to Vtt which tracks Vref.
>
> Regards,
>
> Ihsan
>
>
> On Sat, Apr 28, 2012 at 1:36 PM, Hithesh <hitheshn@xxxxxxxxx> wrote:
>
>> Steve,
>> I would have understood the DC bias, if the ckt was some thing like this -
>> http://images.elektroda.net/8_1335634250.png
>>
>> This ckt is the standard DC bias circuit in BJT ckts.
>> Without the capacitor, the bias won't work.
>>
>> Regards
>> -Hithesh
>>
>>
>>
>> On Sat, Apr 28, 2012 at 5:49 PM, steve weir <weirsi@xxxxxxxxxx> wrote:
>>
>> > I think you should draw the circuit:  The way that it is, and other
>> > configurations that you might try.  See what happens to the DC bias
>> > voltage and current for each combination for both a high and a low
>> > state.  That will answer both your questions.
>> >
>> >
>> > Steve.
>> > On 4/28/2012 5:07 AM, Hithesh wrote:
>> > > Some questions about DDR2 termination -
>> > > Let's say it's a Read operation from Memory to FPGA
>> > >
>> > > DDR2 --->  series termination res--->50 ohm PCB Tx line -->50 ohm
>> > > termination resistor at FPGA to Vtt.
>> > >
>> > > Why should the 50 ohm resistor be terminated to Vtt, why not ground
>> (like
>> > > RF amplifiers)?
>> > >
>> > > Is the DDR2 output voltage 1.8v? If yes, then the max voltage at FPGA
>> > will
>> > > be 0.9v.
>> > >
>> > > Thanks,
>> > > -Hithesh
>> > >
>> > >
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>
>
> --
> Ihsan Erdin
>
>


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