[SI-LIST] Re: DDR2 inteface consultant needed
- From: Chris Johnson <crj@xxxxxxxxxxxxx>
- To: robert.szumowicz@xxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 30 Mar 2007 09:23:15 -0400
Robert,
I usually use termination to Vtt generated by a National LP2995. I
have not used Thevenin termination, but as long as the equivalent
resistance and voltage are the same, the results should be very
similar. I have successfully used the HSTL_I_18 with DDR2 SRAMs on a
Virtex 4. An upcoming design uses a Spartan 3 with Vtt termination, but
that won't be built until May, so I won't be able to comment about what
Spartan I/O looks like until then.
Chris
Robert Szumowicz wrote:
> I do not use DCI, I tried DCI driver as well with the same effect. The
> only difference was that amplitude of output signal was slightly reduced.
>
> I have also tried LVCMOS 1.8V-16mA-Fast and I terminated it to 0.9V at
> the end of a line. The result was similar to SSTL18-I/SSTL18-II driver:
> there was a shelf on the rising edge. I tested LVCMOS25-24-Fast driver
> (another FPGA bank) terminated to 1.25V and I didn't have this issue.
> There was an idea to change Vdd of the bank which suffers the problem
> from 1.8V to 2.5V and to see what happens but it is not straight forward
> (other devices use the same 1.8V) so it wasn't done.
>
> Have you used Spartan3 with 1.8V IOs terminated by Thevenin termination.
>
> thank you for suggestions,
> Robert
>
>
>
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