[SI-LIST] Re: DDR2 inteface consultant needed
- From: <Yasir_Mirza@xxxxxxxx>
- To: <robert.szumowicz@xxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 29 Mar 2007 11:15:02 -0500
#1 is interesting, have you tested on different memory modules from
different vendors. The only thing I can think of is PMOS/NMOS process
differences. I wouldn't be too worried about it since virtually all
memory measurements are done differentially but it is something
interesting to investigate. Ah, another thought came to my mind. What is
your test setup. What scope/probes are you using. I have seen plenty of
bad memory measurements due to bad probing/not having enough bandwidth,
etc.
Yasir Mirza
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Robert Szumowicz
Sent: Thursday, March 29, 2007 4:39 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 inteface consultant needed
Hi all,
I'm designing my first DDR2 memory interface and I have just finished=20
debugging a prototype board and taking measurements of it. Since I don't
have enough experience in the area and my measurements sometimes worry=20
me I would like somebody to assist me in interpreting measurements and=20
to help to improve the layout on the final PCB.
The interface is point to point between FPGA (Spartan3) and DDR2 SODIMM=20
memory module (8 memory chips, 64 data bits) and runs at 150MHz. All=20
lines use a controlled impedance and are routed in offset strip line=20
manner (two signal layers between two planes). Parallel terminations to=20
Vtt are used at both ends of data/strobe lines and in addition there is=20
22R series resistor on the memory module itself. Address and control=20
lines are terminated to Vtt at the end of the line and there is a series
resistor on memory module. By end of the line I mean a SODIMM connector=20
because the real end of the line is on memory module and is not
accessible.
Interface seems to work. I tested a few prototype boards with several=20
memory modules, I ran long term tests even at stressed conditions: 1.8V=20
at its margins, Vref intentionally modified, temperature of chips=20
changed. I am not fully happy of my measurements and not confident if=20
the interface is robust enough.
The things which worry me are the following:
1) Differential clock signals which are terminated differentially (at=20
the memory module) look very strange when observed using single ended=20
probes. One edge of the clock signal is clean, opposite edge of clock=20
signal suffers monotonicity problems. When looking at two signals at the
same time falling edge on one signal form the pair is clean and fast,=20
rising edge of complementary signal is slow and distorted. I would like=20
to know whether it is acceptable if when measuring this clock using=20
differential probe does not show any alarming effects and what side=20
effect may it create?
2)
During write to memory there is a significant crosstalk seen at the=20
memory module. I am especially worried about crosstalk on strobes which=20
comes from data lines and which distorts the strobes in the way that=20
they approach Vref level. I haven't observed Vref+VIH(DC) or=20
Vref-VIL(DC) violation but I am not confident if my test setup shows the
worst case maximum value. I would like to reduce this crosstalk if
possible.
3)
During read from memory I do not observe a clean edges of incoming=20
signals (strobes and data) when measured at FPGA via or at the very end=20
of the line, i.e. at the termination resistor. I suspect that a package=20
transmission line has some effect here. If it is a case then I am unable
to correctly measure signals seen by the receiver. I haven't seen such=20
effect on SI simulations and this effect varies from receiver pin to
pin.
4)
During read from memory I observe a lot of crosstalk on the strobes=20
causing them to be non monotonic and the non monotonicity even crosses=20
Vref level. It seems to be a big issue since strobes are single ended=20
signals in my case and JEDEC standard (JESD79-2B) on figure 80 prohibits
them from being non monotonic between VIL(DC) and VIH(DC). Taking into=20
account that I suspect that I do not see using an oscilloscope the same=20
what receiver's die sees I am unable with my limited experience to judge
if it is acceptable or not. Of course I would like to reduce this=20
crosstalk if possible.
5)
I am observing elevated amount of noise on Vref voltage. It would be=20
great to clean it. First problem is that my noise floor is significant=20
even if I do not measure Vref noise but only a probe pickup which easily
catches noise from neighboring switching voltage regulators. Second=20
doubt is that Vref noise is raised if DDR2 interface is active and I am=20
not sure if I pick up the noise from the air or it is really coupled to=20
my Vref voltage. Third problem with Vref noise measurements is that it=20
greatly varies depending where it is measured (across decoupling=20
capacitor shows the least amount of noise). JEDEC does not say where to=20
measure Vref noise so I am unsure how to measure it to comply with the=20
standard.
I would be grateful if somebody experienced in this are would like to=20
help. I am looking both: a professional help on a consulting basis and=20
advices from the group. I am willing to provide additional detailed=20
information and oscilloscope measurements if somebody is interested in=20
helping.
thank you in advance,
Robert Szumowicz=20
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