[SI-LIST] DDR2 inteface consultant needed
- From: Robert Szumowicz <robert.szumowicz@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 29 Mar 2007 11:38:43 +0200
Hi all,
I'm designing my first DDR2 memory interface and I have just finished
debugging a prototype board and taking measurements of it. Since I don't
have enough experience in the area and my measurements sometimes worry
me I would like somebody to assist me in interpreting measurements and
to help to improve the layout on the final PCB.
The interface is point to point between FPGA (Spartan3) and DDR2 SODIMM
memory module (8 memory chips, 64 data bits) and runs at 150MHz. All
lines use a controlled impedance and are routed in offset strip line
manner (two signal layers between two planes). Parallel terminations to
Vtt are used at both ends of data/strobe lines and in addition there is
22R series resistor on the memory module itself. Address and control
lines are terminated to Vtt at the end of the line and there is a series
resistor on memory module. By end of the line I mean a SODIMM connector
because the real end of the line is on memory module and is not accessible.
Interface seems to work. I tested a few prototype boards with several
memory modules, I ran long term tests even at stressed conditions: 1.8V
at its margins, Vref intentionally modified, temperature of chips
changed. I am not fully happy of my measurements and not confident if
the interface is robust enough.
The things which worry me are the following:
1) Differential clock signals which are terminated differentially (at
the memory module) look very strange when observed using single ended
probes. One edge of the clock signal is clean, opposite edge of clock
signal suffers monotonicity problems. When looking at two signals at the
same time falling edge on one signal form the pair is clean and fast,
rising edge of complementary signal is slow and distorted. I would like
to know whether it is acceptable if when measuring this clock using
differential probe does not show any alarming effects and what side
effect may it create?
2)
During write to memory there is a significant crosstalk seen at the
memory module. I am especially worried about crosstalk on strobes which
comes from data lines and which distorts the strobes in the way that
they approach Vref level. I haven't observed Vref+VIH(DC) or
Vref-VIL(DC) violation but I am not confident if my test setup shows the
worst case maximum value. I would like to reduce this crosstalk if possible.
3)
During read from memory I do not observe a clean edges of incoming
signals (strobes and data) when measured at FPGA via or at the very end
of the line, i.e. at the termination resistor. I suspect that a package
transmission line has some effect here. If it is a case then I am unable
to correctly measure signals seen by the receiver. I haven't seen such
effect on SI simulations and this effect varies from receiver pin to pin.
4)
During read from memory I observe a lot of crosstalk on the strobes
causing them to be non monotonic and the non monotonicity even crosses
Vref level. It seems to be a big issue since strobes are single ended
signals in my case and JEDEC standard (JESD79-2B) on figure 80 prohibits
them from being non monotonic between VIL(DC) and VIH(DC). Taking into
account that I suspect that I do not see using an oscilloscope the same
what receiver's die sees I am unable with my limited experience to judge
if it is acceptable or not. Of course I would like to reduce this
crosstalk if possible.
5)
I am observing elevated amount of noise on Vref voltage. It would be
great to clean it. First problem is that my noise floor is significant
even if I do not measure Vref noise but only a probe pickup which easily
catches noise from neighboring switching voltage regulators. Second
doubt is that Vref noise is raised if DDR2 interface is active and I am
not sure if I pick up the noise from the air or it is really coupled to
my Vref voltage. Third problem with Vref noise measurements is that it
greatly varies depending where it is measured (across decoupling
capacitor shows the least amount of noise). JEDEC does not say where to
measure Vref noise so I am unsure how to measure it to comply with the
standard.
I would be grateful if somebody experienced in this are would like to
help. I am looking both: a professional help on a consulting basis and
advices from the group. I am willing to provide additional detailed
information and oscilloscope measurements if somebody is interested in
helping.
thank you in advance,
Robert Szumowicz
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
