[SI-LIST] Re: DDR Vref Bypassing

  • From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
  • To: "Dale L. Sanders" <Dale@xxxxxxx>, <crjohnson11@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 18 Jul 2005 12:37:56 -0700

Dale

I read the initial post as saying connect a capacitor from Vref to ground
and another capacitor from Vref to Vcc.  Your circuit, if I understand it
correctly, is to connect one half of your X2Y cap from Vref to ground and
the other half from Vcc to ground.  This is not apples apples but apples and
oranges I believe.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

-----Original Message-----
From: Dale L. Sanders [mailto:Dale@xxxxxxx]
Sent: Monday, July 18, 2005 11:47 AM
To: tom@xxxxxxxxxxxxx; crjohnson11@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: DDR Vref Bypassing


Tom,
I agree that standard capacitors that could be an issue of coupling noise
between VDD and Vref.

But if balance is critical, X2Y can be attached in a "Circuit 1"
configuration ... where "A" terminal is attached to VDD and 'B' terminal is
attached to Vref and 'G1' and 'G2' are attached to GND. X2Y would only have
minimal noise coupling between VDD and Vref.

To illustrate this, you can see the data presented at the Freescale
Technology Forum Workshop last month (June) in Orlando, FL (pages 49 - 52).

http://www.x2y.com/x2y/x2y.nsf/1/ftfdecouple.pdf/$FILE/ftfdecouple.pdf



Dale L. Sanders
Application Engineer
X2Y Attenuators, LLC




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Tom Dagostino
Sent: Monday, July 18, 2005 1:16 PM
To: crjohnson11@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR Vref Bypassing

Using capacitors to both ground and Vcc seems to be an invitation to
disaster. The idea of putting a cap to a reference voltage is to keep the AC
impedance low and reference voltage referenced to ground (usually).  Most
supplies have a lot of noise on them when measured to ground.  Adding a cap
from the supply to the reference voltage will inject this unwanted noise
into Vref.  If your circuit is set up such that its reference is Vcc then a
cap to Vcc would be good and a cap to ground would inject noise.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
tom@xxxxxxxxxxxxx
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Christopher R. Johnson
Sent: Monday, July 18, 2005 10:49 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR Vref Bypassing


I have seen references that have Vref  bypass capacitors to both VDD and
GND.  Other references have capacitors only to GND.   Is it really
necessary to have "balanced" capacitors on the Vref lines?  Why?  If the
"balanced" design is desirable, would an X2Y capacitor be a good choice,
since it is "2 capacitors in one"?

Regards,

Chris Johnson
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