Hi Sunil, Use an unity gain buffer(op-amp) for each of the Vref so you could avoid noise. Rgds, Mahabala. >From: steve weir <weirsi@xxxxxxxxxx> >Reply-To: weirsi@xxxxxxxxxx >To: Charles.Grasso@xxxxxxxxxxxx,"'sunil.mekad@xxxxxxxxx'" <sunil.mekad@xxxxxxxxx>,"'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx> >CC: "'billw@xxxxxxxxxxx'" <billw@xxxxxxxxxxx> >Subject: [SI-LIST] Re: DDR Vref Bypassing >Date: Wed, 20 Jul 2005 13:21:26 -0700 > >Phase! Phase! Phase! >At 10:14 AM 7/20/2005 -0600, Grasso, Charles wrote: >>One way is to generate Verve from a separate >>switcher that tracks the DVD ripple. Kind of >>expensive though! >> >>Best Regards >>Charles Grasso >>Senior Compliance Engineer >>Echostar Communications Corp. >>Tel: 303-706-5467 >>Fax: 303-799-6222 >>Cell: 303-204-2974 >>Pager/Short Message: 3032042974@xxxxxxxx >>Email: charles.grasso@xxxxxxxxxxxx; >>Email Alternate: chasgrasso@xxxxxxxx >> >> >> >>-----Original Message----- >>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On >>Behalf Of sunil.mekad@xxxxxxxxx >>Sent: Tuesday, July 19, 2005 10:06 PM >>To: si-list@xxxxxxxxxxxxx >>Cc: billw@xxxxxxxxxxx >>Subject: [SI-LIST] Re: DDR Vref Bypassing >> >> >> >>=0D >>Team, >> >>I have a question here in similar lines to the DDR2 vref. I am trying to >>generate the Vref through a resistor divider approach for the QDR-II and >>Virtex-4 FPGA (that acts as controller). On board I have 3 such interfaces >>(i.e 3 QDR to FPGA single clock mode connection). >> >>I am generating the 0.75V from the 1.5V VDDQ by a resistor divider using 22 >>ohm, 0.1% tol. The devider network is decoupled with 0.01uF caps and 2.2uF >>caps (X7R) to ground. >> >>I am feeding a single such divider network to the 3 FPGA vref inputs (total >>of 18 Vref i/ps). And independent such divider network for each QDR-II >>Srams. (Since the QDR-II SRAM have more HSTL I/P pins than FPGA >>controller)=0D >> >>How do I make my design foolproof so that the ripple in Vref can be avoided >>due to static and AC current requirements? Do I need to split these resistor >>divider to each FPGA just to be sure that the combined AC/Static current >>does not dip my Vref to below desireable levels? >> >>Thanks >>Sunil >> >> >>-----Original Message----- >>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] >>On Behalf Of Bill Wurst >>Sent: Wednesday, July 20, 2005 6:32 AM >>To: si-list@xxxxxxxxxxxxx >>Subject: [SI-LIST] Re: DDR Vref Bypassing >> >>Steve, >> >>I'll try to answer your comments/questions as I understand them (see >>response below). >> >>Regards, >> >> -Bill >> >> >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>steve weir wrote: >>>Bill, I really question where this assumption of average between >>>Vdd=0D and Gnd comes from. The noise level on Vdd at the transmitter >>>is not=0D going to be the same as the instantaneous noise at the >>>receiver, so I=0D don't buy an argument based on the launch. That >>>leaves us with the=0D transmission channel. What percentage of what >>>couples onto the=0D transmitted signal depends on how the board is >>>constructed. >>If the noise on Vdd and Vss at the transmitter propagate to the receiver >>with the same velocity as the signal, then the noise at both the transmitter >>and receiver will be the same but delayed by the flight time. Granted, the >>construction of the board can and will impact this assumption. The premise >>is to make the noise common to both sides of the differential receiver, so >>that the receiver will reject the noise by virtue of its CMRR. At launch, a >>logic '1' will replicate Vdd noise which will be attenuated by terminations >>at both ends and also influenced by any noise on the reference planes as it >>travels to the receiver. Similarly, a logic '0' will replicate Vss noise. >>Trying to make Vref equal to 50% of the difference between the two rails is >>admittedly a compromise and, as you point out, other factors will reduce the >>cancellation further. Yet I fail to see a better alternative. >>>=0D >>>A split filter is in essence a 2Y common mode filter turned inside=0D >>>out. Impedance mismatch gives rise to mode conversion.which throws=0D >>>off that 50% divider assumption for equal value ( data sheet )=0D >>>capacitors. This is why we see 2Y RFI filters with a much bigger X=0D >>>capacitor shunting the two lines together- to swamp out the mode=0D >>>conversion. In the Vref application, the X capacitor is represented=0D >>>by the bypass network from Vcc to Vss. That is really ugly, because=0D >>>it basically says that we need to bypass the heck out of Vdd to get=0D >>>around mode conversion in the Vref bypass caps. >>I agree. This is essentially a 2Y CM filter, and Vdd must be bypassed to >>the greatest extent practical. >>>=0D >>>The two capacitors in an X2Y match so well that even for analog=0D >>>instrumentation they do not need an X capacitor. I have an=0D >>>application note on this in ADI's instrumentation amplifier designer's >> >>>guide, based on real circuit measurements. An X2Y configured as: =0D >>>Terminal A =3D> Vdd, Terminal B =3D> Vss, Terminals G1, and G2 =3D> >>>Vref = >>=0D >>>matches to better than 1%. So, if one is bent on implementing the=0D >>>divider, X2Y capacitors do the job in a way that is basically=0D >>>impossible using separate capacitors to each rail. >>Again, I agree. I hedged in my response because I was unsure of the >>matching that could be achieved with x2y capacitors. >>>=0D >>>If someone is really bent on this divider approach, then X2Y is=0D >>>definitely the way to go. But given that people have been building=0D >>>with it, and apparently it has "worked" despite the mode conversion=0D >>>with regular caps, I really question the validity of the approach in=0D >>>the first place. Do you know what the physical basis for the=0D >>>rationale of the divider is supposed to be? >>Hopefully, unless I've missed something, I've answered this in my response >>to the first paragraph. Please let me know if I haven't. >>>=0D >>>Regards, >>>=0D >>>=0D >>>Steve. >>>=0D >>>At 12:48 PM 7/19/2005 -0400, Bill Wurst wrote: >>>=0D >>>>Chris, >>>> >>>>The answer to your question lies in understanding the function of >>>>the=0D Vref line. DDR, as well as DDR2, utilize differential >>>>receivers to=0D process single-ended inputs that have been generated >>>>by drivers which=0D swing in a balanced fashion around the mid-point >>>>of the VDD/GND >>system. >>>> To properly process these single-ended inputs, the inverting >>>>input=0D of each differential receiver is connected to Vref. The >>>>receivers=0D will work best when Vref equals exactly 0.5*(VDD-GND), >>>>including any=0D noise that is present on the VDD/GND system. The >>>>purpose of placing=0D an equal amount of capacitance from Vref to VDD >>>>and from Vref to GND=0D is to form an ac divider that keeps Vref equal >>>>to 0.5*(VDD-GND) over=0D all frequencies. The capacitance should be >>>>large enough to swamp out=0D any parasitic capacitance that exists >>>>which could imbalance Vref. >>>> >>>>I'll have to hedge on the second question which was "whether an x2y=0D >>>>capacitor is better than two discrete capacitors" since I don't >>>>know=0D enough about x2y devices. Properly configured, an x2y >>>>capacitor could >> >>>>perform better, but the bottom line comes down to the accuracy of >>>>the=0D ac divider. >>>> >>>>Regards, >>>> >>>> -Bill >>>> >>>> >>>> /************************************ >>>> / billw@xxxxxxxxxxx / >>>> / / >>>> / Advanced Electronic Concepts, LLC / >>>> / www.aec-lab.com / >>>> ************************************ >>>>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= >>>>3D= >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D = >>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D >>>>Christopher R. Johnson wrote: >>>> >>>>>I have seen references that have Vref bypass capacitors to both VDD >>and >>>>>GND. Other references have capacitors only to GND. Is it really >>>>>necessary to have "balanced" capacitors on the Vref lines? Why? >>>>>If=0D the "balanced" design is desirable, would an X2Y capacitor be a >>>>>good=0D choice, since it is "2 capacitors in one"? >>>>> >>>>>Regards, >>>>> >>>>>Chris Johnson >>>>>------------------------------------------------------------------ >>------------------------------------------------------------------ >>To unsubscribe from si-list: >>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field >> >>or to administer your membership from a web page, go to: >>//www.freelists.org/webpage/si-list >> >>For help: >>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field >> >>List FAQ wiki page is located at: >> http://si-list.org/wiki/wiki.pl?Si-List_FAQ >> >>List technical documents are available at: >> http://www.si-list.org >> >>List archives are viewable at: =0D >> //www.freelists.org/archives/si-list >>or at our remote archives: >> http://groups.yahoo.com/group/si-list/messages >>Old (prior to June 6, 2001) list archives are viewable at: >> http://www.qsl.net/wb6tpu >> =0D >> >> >> >> >>Confidentiality Notice=0D >> >>The information contained in this electronic message and any attachments to= >>this message are intended for the exclusive use of the addressee(s) and may >>contain confidential or= privileged information. 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