[SI-LIST] Re: DDR SDRAM / Xilinx warning
- From: steve weir <weirsi@xxxxxxxxxx>
- To: james.f.peterson@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 11 Mar 2005 05:21:37 -0800
Jim, I believe that the free DDR controller design kit takes care of the
physical placement restrictions with a UCF file output.
Regards,
Steve.
At 06:14 AM 3/11/2005 -0700, Peterson, James F (FL51) wrote:
>This is a friendly warning to you regarding implementing a DDR SDRAM
>controller in a Virtex2Pro.
>(I usually don't have much to complain about when it comes to Xilinx, they
>have excellent ibis models and their SSO guidelines are based on some
>excellent work on their part.)
>
>Their DDR SDRAM app notes have gaps that need to be filled. In a read
>operation to DDR SDRAM the DQS coming back from the SDRAM is really your
>clock for the data bits as they go into the Xilinx IOB flops. In order for
>DQS to be routed very quickly to those flops it must come in on PAD3 of a
>tile (see XAPP609 & XAPP802). Then it can only be routed to certain IOB
>flops, so you have to make sure your 8 data bits are going to those. AND if
>you have 2 (or more) bytes of SDRAM data (gee, who wouldn't), then you'll
>have 2 or more DQS also. You have to make sure these different DQS signal
>don't both try to go to the same "half" of a tile (a tile has 4 pads :pad0,
>pad1, pad2, pad3 - DQ bits on pad0 and pad1 must use the same DQS as their
>clk - same goes for the pad2 & pad3 pair).
>
>We discovered this late in the game. We had to stop fabrication of the PCB,
>and make the changes in the artwork.....
>
>If you are rolling your own DDR SDRAM controller in a V2P, I would advise
>you to understand the above issues. (Their PACE tool is an effective way to
>check all this.)
>
>regards,
>Jim Peterson
>Honeywell
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