[SI-LIST] Re: DDR SDRAM / Xilinx warning
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: steve weir <weirsi@xxxxxxxxxx>, "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Fri, 11 Mar 2005 06:59:43 -0700
Steve -
your response oversimplifies the issue. these fpga's are huge. it takes time
to finish a design that has millions of gates. more time than it takes to
finish the board. when i have fpgas on a board, the game plan i use is to
have the board fab'd, and in the lab ready to go, by the time the FPGA is
designed. than means i have to lock down pins, as best i can, based on app
notes, etc., way before the logic is designed in the xilinx device.
-jim
-----Original Message-----
From: steve weir [mailto:weirsi@xxxxxxxxxx]
Sent: Friday, March 11, 2005 8:22 AM
To: james.f.peterson@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] DDR SDRAM / Xilinx warning
Jim, I believe that the free DDR controller design kit takes care of the
physical placement restrictions with a UCF file output.
Regards,
Steve.
At 06:14 AM 3/11/2005 -0700, Peterson, James F (FL51) wrote:
>This is a friendly warning to you regarding implementing a DDR SDRAM
>controller in a Virtex2Pro.
>(I usually don't have much to complain about when it comes to Xilinx,
>they have excellent ibis models and their SSO guidelines are based on
>some excellent work on their part.)
>
>Their DDR SDRAM app notes have gaps that need to be filled. In a read
>operation to DDR SDRAM the DQS coming back from the SDRAM is really
>your clock for the data bits as they go into the Xilinx IOB flops. In
>order for DQS to be routed very quickly to those flops it must come in
>on PAD3 of a tile (see XAPP609 & XAPP802). Then it can only be routed
>to certain IOB flops, so you have to make sure your 8 data bits are
>going to those. AND if you have 2 (or more) bytes of SDRAM data (gee,
>who wouldn't), then you'll have 2 or more DQS also. You have to make
>sure these different DQS signal don't both try to go to the same "half"
>of a tile (a tile has 4 pads :pad0, pad1, pad2, pad3 - DQ bits on pad0
>and pad1 must use the same DQS as their clk - same goes for the pad2 & pad3
pair).
>
>We discovered this late in the game. We had to stop fabrication of the
>PCB, and make the changes in the artwork.....
>
>If you are rolling your own DDR SDRAM controller in a V2P, I would
>advise you to understand the above issues. (Their PACE tool is an
>effective way to check all this.)
>
>regards,
>Jim Peterson
>Honeywell
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>//www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
> http://www.si-list.org
>
>List archives are viewable at:
> //www.freelists.org/archives/si-list
>or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
The weirsp@xxxxxxxxxx e-mail address will terminate March 31, 2005.
Please update your address book with weirsi@xxxxxxxxxx
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
