[SI-LIST] Re: DDR SDRAM / Xilinx warning
- From: steve weir <weirsi@xxxxxxxxxx>
- To: james.f.peterson@xxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 11 Mar 2005 07:13:05 -0800
Jim, what I recommend that you do for I/O is run a simple random generator
2^7-1 works fine to insure that cycle by cycle timing works correctly. In
this, it is only necessary to have the most rudimentary function for
direction controls and such, and is fairly easy to stub into the
FPGA. That gets timing for the end-to-end channel including the FPGA I/O
cells that will actually be employed.
Regards,
Steve.
At 08:03 AM 3/11/2005 -0700, Peterson, James F (FL51) wrote:
>I guess my whole point in this original thread was that the limitations in a
>V2P-based DDR SDRRAM controller were not completely documented and to warn
>others to be careful. they've got a lot of good information on this type of
>design, but it's spread out over several app notes and several of the things
>I mentioned are not included yet (I think they will be soon).
>
>by the way, what type of simulation were you referring to when you said :
>"If you are in the unfortunate position of having to commit the boards
>before having a chance to simulate the I/O"
>
>we have started a functional simulation. it's the step where we get a
>synthesized, timing verified, gate-level design completed on the fpga that
>we didn't wait for. it's a big chip, that would probably cost us a few
>months.....also, we've successfully completed board level signal integrity
>sim's and a thorough timing analysis at the board level.....
>
>...so, I don't think we have to get too lucky to escape a second spin |:-)
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
>Behalf Of steve weir
>Sent: Friday, March 11, 2005 9:16 AM
>To: Peterson, James F (FL51); Peterson, James F (FL51);
>si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: DDR SDRAM / Xilinx warning
>
>Jim, I didn't intend to trivialize the task of designing a large complex
>FPGA. I merely wished to point-out a resource that is available. In
>V2/Pro, local clocks, and DPA are both mandatory for DDR at any appreciable
>speed and this imposes a lot of physical restrictions that have been
>incorporated into the design kit. V4 makes this easier, but basically with
>any of the three biggest FPGA vendors, running DDR at speed requires care.
>If you are in the unfortunate position of having to commit the boards before
>having a chance to simulate the I/O, you may be lucky to get away with just
>a second spin.
>
>Regards,
>
>
>Steve.
>At 06:59 AM 3/11/2005 -0700, Peterson, James F (FL51) wrote:
> >Steve -
> >your response oversimplifies the issue. these fpga's are huge. it takes
> >time to finish a design that has millions of gates. more time than it
> >takes to finish the board. when i have fpgas on a board, the game plan
> >i use is to have the board fab'd, and in the lab ready to go, by the
> >time the FPGA is designed. than means i have to lock down pins, as best
> >i can, based on app notes, etc., way before the logic is designed in the
>xilinx device.
> >-jim
> >
> >-----Original Message-----
> >From: steve weir [mailto:weirsi@xxxxxxxxxx]
> >Sent: Friday, March 11, 2005 8:22 AM
> >To: james.f.peterson@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >Subject: Re: [SI-LIST] DDR SDRAM / Xilinx warning
> >
> >Jim, I believe that the free DDR controller design kit takes care of
> >the physical placement restrictions with a UCF file output.
> >
> >Regards,
> >
> >
> >Steve.
> >At 06:14 AM 3/11/2005 -0700, Peterson, James F (FL51) wrote:
> > >This is a friendly warning to you regarding implementing a DDR SDRAM
> > >controller in a Virtex2Pro.
> > >(I usually don't have much to complain about when it comes to Xilinx,
> > >they have excellent ibis models and their SSO guidelines are based on
> > >some excellent work on their part.)
> > >
> > >Their DDR SDRAM app notes have gaps that need to be filled. In a read
> > >operation to DDR SDRAM the DQS coming back from the SDRAM is really
> > >your clock for the data bits as they go into the Xilinx IOB flops. In
> > >order for DQS to be routed very quickly to those flops it must come
> > >in on PAD3 of a tile (see XAPP609 & XAPP802). Then it can only be
> > >routed to certain IOB flops, so you have to make sure your 8 data
> > >bits are going to those. AND if you have 2 (or more) bytes of SDRAM
> > >data (gee, who wouldn't), then you'll have 2 or more DQS also. You
> > >have to make sure these different DQS signal don't both try to go to the
>same "half"
> > >of a tile (a tile has 4 pads :pad0, pad1, pad2, pad3 - DQ bits on
> > >pad0 and pad1 must use the same DQS as their clk - same goes for the
> > >pad2 & pad3
> >pair).
> > >
> > >We discovered this late in the game. We had to stop fabrication of
> > >the PCB, and make the changes in the artwork.....
> > >
> > >If you are rolling your own DDR SDRAM controller in a V2P, I would
> > >advise you to understand the above issues. (Their PACE tool is an
> > >effective way to check all this.)
> > >
> > >regards,
> > >Jim Peterson
> > >Honeywell
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