[SI-LIST] DDR SDRAM
- From: "Ched-Chang Chai" <ched_chang@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 09 May 2002 18:54:35 +0800
Dear SI experts,
For DDR SDRAM using SSTL_2 signaling, is there any particular reason why the
parallel termination resistors must be tied to Vtt=Vdd/2?
Thank you.
--
Regards,
Chai
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